参数资料
型号: LMR10510YSDX/NOPB
厂商: National Semiconductor
文件页数: 9/26页
文件大小: 0K
描述: IC REG BUCK ADJ 1A 6LLP
标准包装: 4,500
系列: SIMPLE SWITCHER®
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 4.5 V
输入电压: 3 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 3MHz
电流 - 输出: 1A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 6-WDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 6-LLP-EP(3x3)
V SW
V IN
SW
D = T ON /T SW
SNVS727B – OCTOBER 2011 – REVISED APRIL 2013
Voltage
0
V D
I L
I PK
Inductor
Current
0
T ON
T SW
T OFF
t
t
Figure 21. Typical Waveforms
SOFT-START
This function forces V OUT to increase at a controlled rate during start up. During soft-start, the error amplifier’s
reference voltage ramps from 0V to its nominal value of 0.6V in approximately 600 μs. This forces the regulator
output to ramp up in a controlled fashion, which helps reduce inrush current.
OUTPUT OVERVOLTAGE PROTECTION
The over-voltage comparator compares the FB pin voltage to a voltage that is 15% higher than the internal
reference V REF . Once the FB pin voltage goes 15% above the internal reference, the internal PMOS control
switch is turned off, which allows the output voltage to decrease toward regulation.
UNDERVOLTAGE LOCKOUT
Under-voltage lockout (UVLO) prevents the LMR10510 from operating until the input voltage exceeds 2.73V
(typ). The UVLO threshold has approximately 430 mV of hysteresis, so the part will operate until V IN drops below
2.3V (typ). Hysteresis prevents the part from turning off during power up if V IN is non-monotonic.
CURRENT LIMIT
The LMR10510 uses cycle-by-cycle current limiting to protect the output switch. During each switching cycle, a
current limit comparator detects if the output switch current exceeds 1.75A (typ), and turns off the switch until the
next switching cycle begins.
THERMAL SHUTDOWN
Thermal shutdown limits total power dissipation by turning off the output switch when the IC junction temperature
exceeds 165°C. After thermal shutdown occurs, the output switch doesn’t turn on until the junction temperature
drops to approximately 150°C.
EN
3.3 P H
VIN
R3
6
EN
U1
SW
3
( 3;′ YHUVLRQ )
L1
VOUT
4, 5
VINA/VIND
1.0 P H
1.8V
2
GND
FB
1
R1
20k
C3
C1
C2
C4
Chf
22 P F
2.2 P F
R2
10k
D1
2.2 P F
22 P F
22 nF
(opt.)
GND
Figure 22. Typical Application Schematic
GND
Copyright ? 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMR10510
9
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