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参数资料
| 型号： | LMX2377UTMX/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20 |
| 封装： | PLASTIC, TSSOP-20 |
| 文件页数： | 20/44页 |
| 文件大小： | 3181K |
| 代理商： | LMX2377UTMX/NOPB |
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Test Setups (Continued)
LMX2377U f
IN Sensitivity Test Setup
20022640
The block diagram above illustrates the setup required to
measure the LMX2377U device’s Main input sensitivity level.
The
same
setup
is
used
for
the
LMX2370TMEB/
LMX2370SLEEB Evaluation Boards. The Aux input sensitiv-
ity test setup is similar to the Main input sensitivity test setup.
The purpose of this test is to measure the acceptable signal
level to the f
IN Main input of the PLL chip. Outside the
acceptable signal range, the feedback divider begins to di-
vide incorrectly and miscount the frequency.
The setup uses an open loop configuration. A power supply
is connected to V
cc and the bias voltage is swept from 2.7V
to 5.5V. The MICROWIRE power supply, Vc, is tied to V
cc.
The Aux PLL is powered down (PWDN Aux Bit = 1). By
means of a signal generator, an RF signal is applied to the
f
IN Main pin. The 3 dB pad provides a 50
match between
the PLL and the signal generator. The OSC
in pin is tied to
V
cc. The N value is typically set to 10000 in Code Loader, i.e.
Main N_CNTRB Word = 312 and Main N_CNTRA Word =
16 for PRE Main Bit = 1. The feedback divider output is
routed to the F
oLD pin by selecting the Main PLL N Divider
Output word (F
oLD Word = 6 or 14) in Code Loader. A
Universal Counter is connected to the F
oLD pin and tied to
the 10 MHz reference output of the signal generator. The
output of the feedback divider is thus monitored and should
be equal to f
IN Main/ N.
The f
IN Main input frequency and power level are then swept
with the signal generator. The measurements are repeated
at different temperatures, namely T
A = -40C, +25C, and
+85C. Sensitivity is reached when the frequency error of the
divided RF input is greater than or equal to 1 Hz. The power
attenuation from the cable and the 3 dB pad must be ac-
counted for. The feedback divider will actually miscount if too
much or too little power is applied to the f
IN Main input.
Therefore, the allowed input power level will be bounded by
the upper and lower sensitivity limits. In a typical application,
if the power level to the f
IN Main input approaches the
sensitivity limits, this can introduce spurs and degradation in
phase noise. When the power level gets even closer to these
limits, or exceeds it, then the Main PLL loses lock.
LMX2377U
www.national.com
27
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