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参数资料
| 型号： | LMX2377UTMX/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20 |
| 封装： | PLASTIC, TSSOP-20 |
| 文件页数： | 34/44页 |
| 文件大小： | 3181K |
| 代理商： | LMX2377UTMX/NOPB |
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Pin Descriptions (Continued)
Pin
Name
Pin No.
20-Pin UTCSP
Pin No.
24-Pin CSP
Pin No.
20-Pin
TSSOP
I/O
Description
f
IN Main
5
6
I
Main prescaler complementary input. For single ended operation,
this pin should be AC grounded. The LMX2377U Main PLL can be
driven differentially when the bypass capacitor is omitted.
GND
6
7
—
Ground for the Main PLL analog circuitry.
OSC
in
7
8
I
Reference oscillator input. It has an approximate V
CC/2 input
threshold and can be driven from an external CMOS or TTL logic
gate.
GND
8
10
9
—
Ground for the Aux PLL digital circuitry, MICROWIRE, F
oLD, and
oscillator circuits.
F
oLD
9
11
10
O
Programmable multiplexed output pin. Functions as a general
purpose CMOS TRI-STATE output, Main/Aux PLL open drain
analog lock detect output, N and R divider output or Fastlock
output, which connects a parallel resistor to the external loop filter.
Clock
10
12
11
I
MICROWIRE Clock input. High impedance CMOS input. Data is
clocked into the 22-bit shift register on the rising edge of Clock.
Data
11
14
12
I
MICROWIRE Data input. High impedance CMOS input. Binary
serial data. The MSB of Data is shifted in first. The last two bits
are the control bits.
LE
12
15
13
I
MICROWIRE Latch Enable input. High impedance CMOS input.
When LE transitions HIGH, Data stored in the shift register is
loaded into one of 4 internal control registers.
Vc
13
16
14
—
Power supply bias for the MICROWIRE circuitry. Must be
≤ V
CC.
Typically connected to the same supply level as the
microprocessor or baseband controller to enable programming at
low voltages.
GND
14
17
15
—
Ground for the Aux PLL analog circuitry.
f
IN Aux
15
18
16
I
Aux PLL prescaler input. Small signal input from the VCO.
GND
16
19
17
—
Ground for the Aux PLL digital circuitry, MICROWIRE, F
oLD, and
oscillator circuits.
D
o Aux
17
20
18
O
Aux PLL charge pump output. the output is connected to an
external loop filter, which drives the input of the VCO.
V
P Aux
18
22
19
—
Aux PLL charge pump power supply. Must be
≥ V
CC.
V
CC
19
23
20
—
Power supply bias for the Aux PLL analog and digital circuits,
F
oLD, and oscillator circuits. VCC may range from 2.7V to 5.5V.
Bypass capacitors should be placed as close as possible to this
pin and be connected directly to the ground plane.
NC
—
1, 9, 13, 21
—
No Connect
LMX2377U
www.national.com
4
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