参数资料
型号: LP3875EMP-ADJ/NOPB
厂商: National Semiconductor
文件页数: 7/20页
文件大小: 0K
描述: IC REG LDO ADJ 1.5A SOT223-5
标准包装: 1
稳压器拓扑结构: 正,可调式
输出电压: 可调
输入电压: 2.5 V ~ 7 V
电压 - 压降(标准): 0.38V @ 1.5A
稳压器数量: 1
电流 - 输出: 1.5A(最小值)
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: TO-261-5,TO-261AB
供应商设备封装: SOT-223-5
包装: 标准包装
产品目录页面: 1292 (CN2011-ZH PDF)
其它名称: LP3875EMP-ADJDKR
SNVS247D – SEPTEMBER 2003 – REVISED APRIL 2013
Application Hints
SETTING THE OUTPUT VOLTAGE
The output voltage is set using the resistors R1 and R2 (see TYPICAL APPLICATION CIRCUIT ). The output is
also dependent on the reference voltage (typically 1.216V) which is measured at the ADJ pin. The output voltage
is given by the equation:
V OUT = V ADJ x ( 1 + R1 / R2)
(1)
This equation does not include errors due to the bias current flowing in the ADJ pin which is typically about 10
nA. This error term is negligible for most applications. If R1 is > 100k ? , a small error may be introduced by the
ADJ bias current.
The tolerance of the external resistors used contributes a significant error to the output voltage accuracy, with 1%
resistors typically adding a total error of approximately 1.4% to the output voltage (this error is in addition to the
tolerance of the reference voltage at V ADJ ).
TURN-ON CHARACTERISTICS FOR OUTPUT VOLTAGES PROGRAMMED TO 2.0V OR BELOW
As Vin increases during start-up, the regulator output will track the input until Vin reaches the minimum operating
voltage (typically about 2.2V). For output voltages programmed to 2.0V or below, the regulator output may
momentarily exceed its programmed output voltage during start up. Outputs programmed to voltages above 2.0V
are not affected by this behavior.
EXTERNAL CAPACITORS
Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be
correctly selected for proper performance.
INPUT CAPACITOR: An input capacitor of at least 10μF is required. Ceramic Ceramic, Tantalum, or Electrolytic
capacitors may be used, and capacitance may be increased without limit
OUTPUT CAPACITOR: An output capacitor is required for loop stability. It must be located less than 1 cm from
the device and connected directly to the output and ground pins using traces which have no other currents
flowing through them (see PCB LAYOUT ).
The minimum value of output capacitance that can be used for stable full-load operation is 10μF, but it may be
increased without limit. The output capacitor must have an ESR value as shown in the stable region of the curve
below. Tantalum capacitors are recommended for the output capacitor.
10
1.0
C OUT > 10 P F
STABLE REGION
0.1
.01
.001
0
1
2
LOAD CURRENT (A)
Figure 16. ESR Curve
C FF (Feed Forward Capacitor)
The capacitor C FF is required to add phase lead and help improve loop compensation. The correct amount of
capacitance depends on the value selected for R1 (see TYPICAL APPLICATION CIRCUIT ). The capacitor
should be selected such that the zero frequency as given by the equation shown below is approximately 45 kHz:
Fz = 45,000 = 1 / ( 2 x π x R1 x C FF )
A good quality ceramic with X5R or X7R dielectric should be used for this capacitor.
(2)
Copyright ? 2003–2013, Texas Instruments Incorporated
Product Folder Links: LP3875-ADJ
7
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