参数资料
型号: LP62S4096EU-70LLT
厂商: AMIC Technology Corporation
英文描述: 512K X 8 BIT LOW VOLTAGE CMOS SRAM
中文描述: 为512k × 8位低电压CMOS的SRAM
文件页数: 10/14页
文件大小: 162K
代理商: LP62S4096EU-70LLT
LP62S4096E-T Series
(January, 2002, Version 2.0)
5
AMIC Technology, Inc.
Truth Table
Mode
CE1
CE2
OE
WE
I/O Operation
Supply Current
Standby
H
X
High Z
ISB, ISB1
Standby
X
L
X
High Z
ISB, ISB1
Output Disable
L
H
High Z
ICC, ICC1, ICC2
Read
L
H
L
H
DOUT
ICC, ICC1, ICC2
Write
L
H
X
L
DIN
ICC, ICC1, ICC2
Note: X = H or L
Capacitance (TA = 25
°C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
CIN*
Input Capacitance
6
pF
VIN = 0V
CI/O*
Input/Output Capacitance
8
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = -25
°C to + 85°C, VCC = 2.7V to 3.6V)
Symbol
Parameter
LP62S4096E-55LLT
LP62S4096E-70LLT
Unit
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
55
-
70
-
ns
tAA
Address Access Time
-
55
-
70
ns
tACE1, tACE2
Chip Enable Access Time
-
55
-
70
ns
tOE
Output Enable to Output Valid
-
30
35
ns
tCLZ1, tCLZ2
Chip Enable to Output in Low Z
10
-
10
-
ns
tOLZ
Output Enable to Output in Low Z
5
-
5
-
ns
tCHZ1, tCHZ2
Chip Disable to Output in High Z
0
20
0
25
ns
tOHZ
Output Disable to Output in High Z
0
20
0
25
ns
tOH
Output Hold from Address Change
5
-
5
-
ns
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LP62S4096EV-55LLI 512K X 8 BIT LOW VOLTAGE CMOS SRAM
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相关代理商/技术参数
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LP62S4096EV-55LLI 制造商:AMICC 制造商全称:AMIC Technology 功能描述:512K X 8 BIT LOW VOLTAGE CMOS SRAM
LP62S4096EV-55LLT 制造商:AMICC 制造商全称:AMIC Technology 功能描述:512K X 8 BIT LOW VOLTAGE CMOS SRAM
LP62S4096EV-70LLI 制造商:AMICC 制造商全称:AMIC Technology 功能描述:512K X 8 BIT LOW VOLTAGE CMOS SRAM
LP62S4096EV-70LLT 制造商:AMICC 制造商全称:AMIC Technology 功能描述:512K X 8 BIT LOW VOLTAGE CMOS SRAM
LP62S4096EX-55LLI 制造商:AMICC 制造商全称:AMIC Technology 功能描述:512K X 8 BIT LOW VOLTAGE CMOS SRAM