参数资料
| 型号： | LT1913IDD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 18/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3.5A 10DFN |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.79 V ~ 25 V |
| 输入电压： | 3.6 V ~ 25 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz ~ 2.4MHz |
| 电流 - 输出： | 3.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 10-DFN（3x3） |
LT1913
APPLICATIONS INFORMATION
to prevent this overshoot. Figure 9 shows the waveforms
that result when an LT1913 circuit is connected to a 24V
supply through six feet of 24-gauge twisted pair. The
?rst plot is the response with a 4.7μF ceramic capacitor
at the input. The input voltage rings as high as 50V and
the input current peaks at 26A. A good solution is shown
in Figure 9b. A 0.7 resistor is added in series with the
input to eliminate the voltage overshoot (it also reduces
the peak input current). A 0.1μF capacitor improves high
frequency ?ltering. For high input voltages its impact on
ef?ciency is minor, reducing ef?ciency by 1.5 percent for
a 5V output at full load operating from 24V.
CLOSING SWITCH
High Temperature Considerations
The PCB must provide heat sinking to keep the LT1913
cool. The Exposed Pad on the bottom of the package must
be soldered to a ground plane. This ground should be tied
to large copper layers below with thermal vias; these lay-
ers will spread the heat dissipated by the LT1913. Place
additional vias can reduce thermal resistance further. With
these steps, the thermal resistance from die (or junction)
to ambient can be reduced to JA = 35°C/W or less. With
100 LFPM air?ow, this resistance can fall by another 25%.
Further increases in air?ow will lead to lower thermal re-
DANGER
SIMULATES HOT PLUG
I IN
V IN
LT1913
V IN
20V/DIV
RINGING V IN MAY EXCEED
+
4.7μF
ABSOLUTE MAXIMUM RATING
LOW
IMPEDANCE
ENERGIZED
24V SUPPLY
+
STRAY
INDUCTANCE
DUE TO 6 FEET
(2 METERS) OF
TWISTED PAIR
0.7Ω
0.1μF
LT1913
4.7μF
LT1913
I IN
10A/DIV
(9a)
V IN
20V/DIV
I IN
10A/DIV
(9b)
V IN
20V/DIV
20μs/DIV
20μs/DIV
+
22μF
35V
+
4.7μF
AI.EI.
I IN
10A/DIV
(9c)
20μs/DIV
1913 F09
Figure 9. A Well Chosen Input Network Prevents Input Voltage Overshoot and
Ensures Reliable Operation when the LT1913 is Connected to a Live Supply
1913f
18
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