参数资料
型号: LT1939EDD#PBF
厂商: Linear Technology
文件页数: 17/24页
文件大小: 349K
描述: IC REG DL BUCK/LINEAR 12DFN
标准包装: 121
拓扑: 降压(降压)(1),线性(LDO)(1)
功能: 任何功能
输出数: 2
频率 - 开关: 500kHz ~ 2.4MHz
电压/电流 - 输出 1: 0.8 V ~ 24.25 V,2A
电压/电流 - 输出 2: 0.8 V ~ 24.25 V,1A
带 LED 驱动器:
带监控器:
带序列发生器:
电源电压: 3 V ~ 25 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 12-WFDFN 裸露焊盘
供应商设备封装: 12-DFN
包装: 管件
LT1939
17
1939f
is much lower than the switching frequency. A phase lead
capacitor (C
PL
) across the feedback divider may improve
the transient response.
Synchronization
The R
T
/SYNC pin can be used to synchronize the LT1939
to an external clock source. Driving the R
T
/SYNC resistor
with a clock source triggers the synchronization detection
circuitry. Once synchronization is detected, the rising edge
of SW will be synchronized to the rising edge of the R
T
/SYNC
pin signal. An AGC loop will adjust slope compensation
to avoid subharmonic oscillation.
The synchronizing clock signal input to the LT1939 must
have a frequency between 250kHz and 2.5MHz, a duty
cycle between 20% and 80%, a low state below 0.5V and
a high state above 1.6V. Synchronization signals outside
of these parameters will cause erratic switching behavior.
The R
T
/SYNC resistor should be set such that the free
running frequency ((V
RT/SYNC
  V
SYNCLO
)/R
RT/SYNC
) is
approximately equal to the synchronization frequency. If
the synchronization signal is halted, the synchronization
detection circuitry will timeout in typically 10約 at which
time the LT1939 reverts to the free-running frequency
based on the current through R
T
/SYNC. If the R
T
/SYNC
resistor is held above 1.6V at any time, switching will be
disabled.
If the synchronization signal is not present during regu-
lator start-up (for example, the synchronization circuitry
is powered from the regulator output) the R
T
/SYNC pin
must see an equivalent resistance to ground between 15k
and 200k until the synchronization circuitry is active for
proper start-up operation.
If the synchronization signal powers up in an undetermined
state (V
OL
, V
OH
, Hi-Z), connect the synchronization clock
to the LT1939 as shown in Figure 7. The circuit as shown
will isolate the synchronization signal when the output
voltage is below 90% of the regulated output. The LT1939
will start-up with a switching frequency determined by the
resistor from the R
T
/SYNC pin to ground.
APPLICATIONS INFORMATION
Figure 6. Model for Loop Response
Figure 7. Synchronous Signal Powered from Regulators Output
If the synchronization signal powers up in a low impedance
state (V
OL
), connect a resistor between the R
T
/SYNC pin
and the synchronizing clock. The equivalent resistance
seen from the R
T
/SYNC pin to ground will set the start-up
frequency.
If the synchronization signal powers up in a high impedance
state (Hi-Z), connect a resistor from the R
T
/SYNC pin to
ground. The equivalent resistance seen from the R
T
/SYNC
pin to ground will set the start-up frequency.
If the synchronization signal changes between high and
low impedance states during power up (V
OL
, Hi-Z), connect
SW
LT1939
FB
V
C
0.8V
C
F
C
PL
V
OUT1
C1
C1
1939 F06
C
C
R
C
R1
ESR
TANTALUM
OR
POLYMER
CERAMIC
R2
4M
ERROR AMP
g
m
= 250糾hos
CURRENT MODE
POWER STAGE
g
m
 = 3mho
12
8
5
LT1939
SYNCHRONIZATION
CIRCUITRY
LDRV
PG
R
T
/SYNC
1939 F07
V
CC
CLK
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