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| 型号： | LT1952MPGN#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 560 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | 0.150 INCH, LEAD FREE, PLASTIC, SSOP-16 |
| 文件页数： | 17/28页 |
| 文件大小： | 357K |
| 代理商： | LT1952MPGN#PBF |
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LT1952/LT1952-1
24
19521fe
Bus Converter: Optimum Output Voltage Tolerance
The Bus Converter applications shown on page 1 and in
Figure 16, provide semi-regulated isolated outputs without
theneedforanoptocoupler,optocouplerdriver,referenceor
feedbacknetwork.TheLT1952/LT1952-1Volt-Secondclamp
adjusts switch duty cycle inversely proportional to input
voltage to provide an output voltage that is regulated against
input line variations. Some bus converters use a switch duty
cycle limit which causes output voltage variation of typically
±33% over a 2:1 input voltage range. The LT1952/LT1952-1
typically provide a
±10% output variation for the same input
variation.Typicaloutputtoleranceisfurtherimprovedforthe
LT1952 by inserting a resistor from the system input voltage
to the SS_MAXDC pin (Rx in Figure 19).
The LT1952/LT1952-1 electrical specifications for the OUT
Max Duty Cycle Clamp show typical switch duty cycle to
move from 72% to 33% for a 2x change of input voltage
(SS_MAXDC pin=1.84V).Sinceoutputvoltageregulation
follows VINDutyCycle,aswitchdutycyclechangeof
72% to 36% (for a 2x input voltage change) provides
minimal output voltage variation for the LT1952/LT1952-1
bus converter. To achieve this, an SS_MAXDC pin voltage
increase of 1.09x (36/33) would be required at high input
line. A resistor Rx inserted between the SS_MAXDC pin
andsysteminputvoltage(Figure19)increasesSS_MAXDC
voltage as input voltage increases, minimizing output
voltage variation over a 2:1 input voltage change.
The following steps determine values for Rx, RT and RB:
(1)Program switch duty cycle at minimum system input
voltage (VS(MIN))
(a)RT(1) = 10k (minimum allowed to still guarantee soft-
start pull-down)
APPLICATIONS INFORMATION
(b)Select switch duty cycle for the Bus Converter for a
givenoutputvoltageatVS(MIN)andcalculateSS_MAXDC
voltage(SS1)(SeeApplicationsInformation“Program-
ming Maximum Duty Cycle Clamp”)
(c)Calculate RB(1)=[SS1/(2.5–SS1)]RT(1)
(2)Calculate Rx:
Rx = ([VS(MAX) – VS(MIN)]/[SS1(X–1)])RTHEV(1)
RTHEV(1) = RB(1)RT(1)/(RB(1) + RT(1)), X = ideal duty
cycle (VS(MAX))/actual duty cycle (VS(MAX))
(3)The addition of Rx causes an increase in the original
programmed SS_MAXDC voltage SS1. A new value for
RB(1)shouldbecalculatedtoprovidealowerSS_MAXDC
voltage (SS2) to correct for this offset:
(a)SS2 = SS1 – [(VS(MIN)–SS1)RTHEV(1)/Rx]
(b)RB(2)=[SS2/(2.5–SS2)]RT(1)
(4)The thevinin resistance RTHEV(1) used to calculate Rx
should be re-established for RT and RB:
(a) RB (final value) = RB(2)(RTHEV(1)/RTHEV(2))
(b) RT (final value) = RT(1)(RTHEV(1)/RTHEV(2))
where RTHEV(2) = RB(2)RT(1)/(RB(2) + RT(1))
Example:
For a Bus Converter running from 36V to 72V input,
VS(MIN) = 36V, VS(MAX) = 72V.
choose RT(1) = 10k, SS_MAXDC = SS1 = 1.84V (for 72%
duty cycle at VS(MIN) = 36V)
RB(1)=[1.84V/(2.5V–1.84V)]10k=28k
RTHEV(1)=[28k10k/(28k+10k)]=7.4k
SS_MAXDC correction = 36%/33% = 1.09
Rx=[(72V–36V)/(1.840.09)]7.4k=1.6M
SS2=1.84–[(36V–1.84)7.4k/1.6M]=1.682V
RB(2)=[1.682/(2.5–1.682)]10k=20.6k
RTHEV(2)=[20.6k10k/(20.6k+10k)]=6.7k
RTHEV(1)/RTHEV(2) = 7.4k/6.7k = 1.104
RB(finalvalue)=20.6k1.104=22.7k(choose22.6k)
RT(finalvalue)=10k1.104=11k
SYSTEM
INPUT VOLTAGE
VOLT-SECOND
CLAMP INPUT
VOLT-SECOND
CLAMP ADJUST INPUT
1952 F19
SD_VSEC
SS_MAXDC
VREF
LT1952/
LT1952-1
R1
Rx
R2
RB
RT
Figure 19. Optimal Programming of Maximum Duty
Cycle Clamp for Bus Converter Applications (Adding Rx)
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