参数资料
| 型号： | LT3070EUFD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 19/28页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ 5A 28QFN |
| 产品培训模块： | LT3070 - 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator |
| 标准包装： | 2,500 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 0.8 V ~ 1.8 V |
| 输入电压： | 0.95 V ~ 3 V |
| 电压 - 压降（标准）： | 0.085V @ 5A |
| 稳压器数量： | 1 |
| 电流 - 输出： | 5A |
| 电流 - 限制（最小）： | 5.1A |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（4x5） |
| 包装： | 带卷 (TR) |
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LT3070
APPLICATIONS INFORMATION
Lo-Z
4.7μF
inductance by using a parallel capacitor combination.
A suitable methodology must control this paralleling as
capacitors with the same self-resonant frequency, f R , will
form a tank circuit that can induce ringing of their own
accord. Small amounts of ESR (5mΩ to 20mΩ) have some
benefit in dampening the resonant loop, but higher ESRs
degrade the capacitor response to transient load steps
with rise/fall times less than 1μs. The most area efficient
parallel capacitor combination is a graduated 4/2/1 scale
of f R of the same case size. Under these conditions, the
individual ESLs are relatively uniform, and the resonance
peaks are deconstructively spread beyond the regulator
bandwidth. The recommended parallel combination that
approximates 15μF is 10μF + 4.7μF + 2.2μF. Capacitors
with case sizes larger than 0805 have higher ESL and
lower ESR (<5mΩ). Therefore, more capacitors with
smaller values (<10μF) must be chosen. Users should
consider new generation, low inductance capacitors to
push out f R and maximize stability. Refer to the surface
mount ceramic capacitor manufacturer’s data sheets for
capacitor specifications. Figure 3 illustrates an optimum
PCB layout for the parallel output capacitor combination,
but also illustrates the GND connection between the IN
capacitor and the OUT capacitors to minimize the AC
GND loop for fast load transients. This tight bypassing
connection minimizes EMI and optimizes bypassing.
Many of the applications in which the LT3070 excels,
such as FPGA, ASIC processor or DSP supplies, typically
require a high frequency decoupling capacitor network for
the device being powered. This network generally consists
of many low value ceramic capacitors in parallel. In some
LT3070
SENSE
IN OUT
GND
INPUT
2.2μF LOAD PLANE
47μF
10μF
3070 F03
applications, this total value of capacitance may be close
to the LT3070’s minimum 15μF capacitance requirement.
This may reduce the required value of capacitance directly
at the LT3070’s output. Multiple low value capacitors in
parallel present a favorable frequency characteristic that
pushes many of the parasitic poles/zeroes beyond the
LT3070’s unity-gain crossover frequency. This technique
illustrates the method that extracts the full bandwidth
performance of the LT3070.
Give additional consideration to the use of ceramic capaci-
tors. Ceramic capacitors are manufactured with a variety of
dielectrics, each with different behavior across temperature
and applied voltage. The most common dielectrics used
are specified with EIA temperature characteristic codes of
Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are
good for providing high capacitances in a small package,
but they tend to have strong voltage and temperature
coefficients as shown in Figures 4 and 5. When used with
a 5V regulator, a 16V 10μF Y5V capacitor can exhibit an
effective value as low as 1μF to 2μF for the DC bias voltage
applied and over the operating temperature range. The X5R
and X7R dielectrics result in more stable characteristics
and are more suitable for use as the output capacitor.
The X7R type has better stability across temperature,
while the X5R is less expensive and is available in higher
values. Care still must be exercised when using X5R and
X7R capacitors; the X5R and X7R codes only specify
operating temperature range and maximum capacitance
change over temperature. Capacitance change due to
DC bias with X5R and X7R capacitors is better than Y5V
and Z5U capacitors, but can still be significant enough to
drop capacitor values below appropriate levels. Capacitor
DC bias characteristics tend to improve as component
case size increases, but expected capacitance at operat-
ing voltage should be verified. Voltage and temperature
coefficients are not the only sources of problems. Some
ceramic capacitors have a piezoelectric response. A piezo-
electric device generates voltage across its terminals due
to mechanical stress, similar to the way a piezoelectric
microphone works. For a ceramic capacitor the stress
can be induced by vibrations in the system or thermal
transients.
Figure 3. Example PCB Layout
3070fb
For more information www.linear.com/LT3070
19
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LT3070IUFD | 制造商:LINER 制造商全称:Linear Technology 功能描述:5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator |
| LT3070IUFD#PBF | 功能描述:IC REG LDO ADJ 5A 28QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:1 系列:- 稳压器拓扑结构:正，固定式 输出电压:8V 输入电压:10.5 V ~ 23 V 电压 - 压降（标准）:1.7V @ 40mA 稳压器数量:1 电流 - 输出:100mA（最小值） 电流 - 限制（最小）:- 工作温度:0°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:剪切带 (CT) 产品目录页面:1075 (CN2011-ZH PDF) 其它名称:296-24390-1 |
| LT3070IUFD#TRPBF | 功能描述:IC REG LDO ADJ 5A 28QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:3,000 系列:- 稳压器拓扑结构:正，固定式 输出电压:2.5V 输入电压:2.5 V ~ 5.5 V 电压 - 压降（标准）:- 稳压器数量:1 电流 - 输出:300mA（最小值） 电流 - 限制（最小）:360mA 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SOT-23-5 细型，TSOT-23-5 供应商设备封装:TSOT-23-5 包装:带卷 (TR) |
| LT3070IUFDPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator |
| LT3070IUFDTR | 制造商:LINER 制造商全称:Linear Technology 功能描述:5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator |
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