参数资料
型号: LT3580MPMS8E#TRPBF
厂商: Linear Technology
文件页数: 11/28页
文件大小: 0K
描述: IC REG BOOST INV SEPIC 2A 8MSOP
标准包装: 2,500
类型: 升压(升压),反相,Sepic
输出数: 1
输入电压: 2.5 V ~ 32 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 2.5MHz
电流 - 输出: 2A
同步整流器:
工作温度: -55°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 8-MSOP-EP
LT3580
APPLICATIONS INFORMATION
Output Pole: P1 =
Error Amp Pole: P2 =
Error Amp Zero: Z1 =
? V C ? I ? V OUT ? V FB
( g ma ? R 0 ) ? g mp ? ? η ? V V IN
? R L ? 0.5R2
? ? ? R1 + 0.5R2
Compensation—Theory
Like all other current mode switching regulators, the
LT3580 needs to be compensated for stable and efficient
operation. Two feedback loops are used in the LT3580—
a fast current loop which does not require compensation,
and a slower voltage loop which does. Standard bode plot
analysis can be used to understand and adjust the voltage
feedback loop.
As with any feedback loop, identifying the gain and phase
contribution of the various elements in the loop is critical.
Figure 4 shows the key equivalent elements of a boost
converter. Because of the fast current control loop, the
power stage of the IC, inductor and diode have been replaced
by a combination of the equivalent transconductance
amplifier g mp and the current controlled current source
(which converts I VIN to η V IN /V OUT ? I VIN ). g mp acts as
a current source where the peak input current, I VIN , is
proportional to the VC voltage. η is the efficiency of the
From Figure 4, the DC gain, poles and zeros can be cal-
culated as follows:
2
2 ? π ? R L ? C OUT
1
2 ? π ? ?? R O + R C ?? ? C C
1
2 ? π ? R C ? C C
DC Gain:
(Breaking Loop at FB Pin)
A DC = A OL (0) = ? VIN ? ? =
? V FB ? V C ? I VIN ? V OUT
?
? OUT 2
switching regulator, and is typically about 88%.
Note that the maximum output currents of g mp and g ma are
finite. The limits for g mp are in the Electrical Characteristics
section (switch current limit), and g ma is nominally limited
to about ±12μA.
ESR Zero: Z2 =
RHP Zero: Z3 =
1
2 ? π ? R ESR ? C OUT
V IN 2 ? R L
2 ? π ? V OUT 2 ? L
g mp
I VIN
V OUT
High Frequency Pole: P3 >
f S
3
? V IN
V OUT
?I VIN
C PL
R ESR
C OUT
R L
Phase Lead Zero: Z4 =
1
2 ? π ? R1? C PL
C F
R C
C C
V C
R O
g ma
+
1.215V
REFERENCE
R2
R2
FB
R1
3580 F04
Phase Lead Pole: P4 =
2? π ?
1
R1?
R1 +
R2
2 ?C PL
R2
2
C C : COMPENSATION CAPACITOR
Error Amp Filter Pole:
2? π ? C
,C F < C
C OUT : OUTPUT CAPACITOR
C PL : PHASE LEAD CAPACITOR
C F : HIGH FREQUENCY FILTER CAPACITOR
g ma : TRANSCONDUCTANCE AMPLIFIER INSIDE IC
g mp : POWER STAGE TRANSCONDUCTANCE AMPLIFIER
R C : COMPENSATION RESISTOR
P5 =
1
R ?R O
R C +R O
? C F
C
10
R L : OUTPUT RESISTANCE DEFINED AS V OUT DIVIDED BY I LOAD(MAX)
R O : OUTPUT RESISTANCE OF g ma
R1, R2: FEEDBACK RESISTOR DIVIDER NETWORK
R ESR : OUTPUT CAPACITOR ESR
Figure 4. Boost Converter Equivalent Model
The current mode zero (Z3) is a right-half plane zero
which can be an issue in feedback control design, but is
manageable with proper external component selection.
3580fg
11
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