参数资料
型号: LT3640IFE#TRPBF
厂商: Linear Technology
文件页数: 13/24页
文件大小: 0K
描述: IC REG BUCK FIX/ADJ DL 28TSSOP
标准包装: 2,000
类型: 降压(降压)
输出类型: 两者兼有
输出数: 2
输出电压: 1.8V,3.3V,可调
输入电压: 2.5 V ~ 35 V
PWM 型: 电流模式,混合
频率 - 开关: 500kHz ~ 2MHz
电流 - 输出: 1.1A,1.3A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 28-TSSOP 裸露焊盘
LT3640
APPLICATIONS INFORMATION
V IN ( MAX ) = ? OUT 1
? ? ? V D CE
? V + V D ?
V IN 2 ( MAX ) ≈
V OUT 1 + V D
f S
V IN 2 ( MIN ) ≈
? ? 1 – OUT 1
( V OUT 1 + V D ) ? V + V D ?
? ?
? I L 1 =
? I L
I L ( PEAK ) = I OUT ( MAX ) +
ThemaximumV IN shouldnotexceedtheabsolutemaxi-
mum rating. For fixed frequency operation, the maximum
V IN is:
+ V
? DC MIN
Note that the high voltage buck will still regulate at an input
voltage that exceeds V IN(MAX) (up to 35V). However, the
switching frequency will be lowered to satisfy the equa-
tion (Figure 1).
Once the input voltage reaches 36.5V, an internal overvoltage
lockout (OVLO) circuit is triggered to disable switching ac-
tion (Figure 2). Without switching, the LT3640 can sustain
V IN voltage transients up to 55V for one second.
V IN2 Voltage Range
The low voltage synchronous channel operates from
the V IN2 pin. The V IN2 pin can be connected to either an
independent voltage supply or the high voltage channel
output for a two-stage power regulator.
In either configuration, if the high voltage channel is over-
loaded and pulled out of regulation, the low voltage channel
will be disabled. The SS2 pin will be discharged as well.
The minimum V IN2 voltage to regulate output voltage is:
V OUT 2
DC MAX
Where DC MAX is the maximum duty cycle (refer to
the Switching Frequency section). If V IN2 is below the
SW1
10V/DIV
I L1
0.5A/DIV
calculated minimum voltage, the output will fall out of
regulation.
The maximum V IN2 for fixed frequency operation is:
V OUT 2
DC MIN
Where DC MIN is the minimum duty cycle (refer to the Switch-
ing Frequency section). For voltage that exceeds V IN2(MAX)
(up to 5.5V), the low voltage channel exhi-bits pulse-skip-
ping behavior, and the output ripple will increase.
Inductor Selection
Inductor selection involves inductance, saturation current,
series resistance (DCR) and magnetic loss.
The inductance for the high voltage channel is:
L 1 = 1 . 7 ?
where V OUT1 is high voltage channel output voltage, V D
is the forward voltage drop of the catch diode, and f S is
the switching frequency. For example, 3.3μH is a reason-
able inductance for a 3.3V output with 2MHz switching
frequency.
Once the inductance is selected, the inductor current ripple
and peak current can be calculated:
I L 1 ? f S ? V IN
2
I L1
2A/DIV
200ns/DIV
10μs/DIV
3640 F01
V IN = 30V R T SET = 2MHz
V OUT1 = 3.3V/0.2A
Figure 1. Lower Switching Frequency Occurs in High
Voltage Channel When Required On-Time Is Below 50ns
V IN
20V/DIV
55V PK , 40V, 15V
3640 F02
Figure 2. V IN Overvoltage Lockout
3640f
  
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