参数资料
| 型号： | LT3682IDD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 18/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 1A 12DFN |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 20 V |
| 输入电压： | 3.6 V ~ 36 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 250kHz ~ 2.2MHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 12-DFN |
LT3682
APPLICATIONS INFORMATION
BOOST and BD Pin Considerations
Capacitor C3 and the internal boost Schottky diode (see
the Block Diagram) are used to generate a boost volt-
age that is higher than the input voltage. In most cases
a 0.22μF capacitor will work well. Figure 5 shows three
ways to arrange the boost circuit. The BOOST pin must
be more than 2.3V above the SW pin for best ef?ciency.
For outputs of between 3V and 8V, the standard circuit
(Figure 5a) is best. For outputs between 2.8V and 3V, use
The minimum operating voltage of an LT3682 applica-
tion is limited by the minimum input voltage and by the
maximum duty cycle as outlined previously. For proper
startup, the minimum input voltage is also limited by the
boost circuit. If the input voltage is ramped slowly, or the
LT3682 is turned on with its RUN/SS pin when the output
V OUT
BD
BOOST
a 1μF boost capacitor. A 2.5V output presents a special
V IN
V IN
LT3682
C3
case because it is marginally adequate to support the
boosted drive stage while using the internal boost diode.
For reliable BOOST pin operation with 2.5V outputs use
SW
DA
D1
a good external Schottky diode (such as the ON Semi
MBR0540), and a 1μF boost capacitor (see Figure 5b).
GND
PGND
For lower output voltages the boost diode can be tied to
the input (Figure 5c), or to another supply greater than
2.8V. Keep in mind that a minimum input voltage of 4.3V
(5a) For V OUT > 2.8V; V IN(MIN) = 4.3V if V OUT < 3V
V OUT
is required if the voltage at the BD pin is smaller than 3V.
Tying BD to V IN reduces the maximum input voltage to
BD
BOOST
D2
25V. The circuit in Figure 5a is more ef?cient because the
V IN
V IN
LT3682
C3
BOOST pin current and BD pin quiescent current come
from a lower voltage source. You must also be sure that
the maximum voltage ratings of the BOOST and BD pins
SW
DA
D1
are not exceeded.
As mentioned, a minimum of 2.5V across the BOOST
GND
PGND
capacitor is required for proper operation of the internal
BOOST circuitry to provide the base current for the power
(5b) For 2.5V < V OUT < 2.8V; V IN(MIN) = 4.3V
NPN switch. For BD pin voltages higher than 3V, the excess
voltage across the BOOST capacitor does not bring an
BD
BOOST
V OUT
increase in performance but dissipates additional power in
the internal BOOST circuitry instead. The BOOST circuitry
tolerates reasonable amounts of power, however excessive
V IN
V IN
LT3682
SW
C3
D1
power dissipation on this circuitry may impair reliability. For
DA
reliable operation, use no more than 8V on the BD pin for
the circuit in Figure 5a. For higher output voltages, make
GND
PGND
sure that there is no more than 8V at the BD pin either by
connecting it to another available supply higher than 3V or
by using a Zener diode between V OUT and BD to maintain
the BD pin voltage between 3V and 8V.
(5c) For V OUT < 2.5V; V IN(MAX) = 25V
3682 F05
Figure 5. Three Circuits For Generating The Boost Voltage
3682f
18
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