参数资料
型号: LT3686HDD#TRPBF
厂商: Linear Technology
文件页数: 10/28页
文件大小: 0K
描述: IC REG BUCK ADJ 1.2A 10DFN
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 30 V
输入电压: 3.6 V ~ 37 V
PWM 型: 电流模式
频率 - 开关: 300kHz ~ 2.5MHz
电流 - 输出: 1.2A
同步整流器:
工作温度: -40°C ~ 150°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 10-DFN(3x3)
LT3686
APPLICATIONS INFORMATION
R1 = R2 ? OUT – 1 ?
FBResistorNetwork
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the 1% resis-
tors according to:
? V ?
? 0.8V ?
45
40
35
30
25
20
15
R2 should be 20k or less to avoid bias current errors.
Reference designators refer to the Block Diagram.
10
5
0
0
10
20 30
40
50
Programmable Undervoltage Lockout
EN/UVLO (V)
3686 F02
? V IN ?
R4 = R5 ? – 1 ?
V OUT + V D
TheEN/UVLOpincanbeprogrammedbyanexternalre-
sistor divider between V IN and the EN/UVLO pin. Choose
the resistors according to:
? 1.27V ?
R4 also sets the hysteresis voltage for the programmable
UVLO:
  Hysteresis = R4 ? 2.4μA
Once V IN drops below the programmed voltage, the LT3686
will enter a low quiescent current state (I Q ≈ 15μA). To
shutdown the LT3686 completely (I Q < 1μA), reduce EN/
UVLO pin voltage to below 0.4V.
10000
1000
Figure 2. EN/UVLO Pin Current
Input Voltage Range
The input voltage range for the LT3686 applications depends
on the output voltage and on the absolute maximum ratings
of the V IN and BOOST pins. The minimum input voltage
is determined by either the LT3686’s minimum operating
voltage of 3.6V, or by its maximum duty cycle.
The duty cycle is the fraction of time that the internal switch
is on and is determined by the input and output voltages:
DC =
V IN – V SW + V D
Where V D is the forward voltage drop of the catch diode
(~0.4V) and V SW is the voltage drop of the internal switch
(~0.67V at maximum load). This leads to a minimum input
voltage of:
100
10
V IN(MIN) =
V OUT + V D
DC MAX
– V D + V SW
1
0.1
0
1
2
3 4 5
EN/UVLO (V)
6
7
8
DC MAX can be adjusted with frequency.
The boost capacitor is charged with the energy stored in
the inductor, the circuit will rely on some minimum load
current to sustain the charge across the boost capacitor.
3686 F01
Figure 1. I Q vs V EN/UVLO (V IN = 10V)
3686fc
10
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