参数资料
型号: LT3724IFE#PBF
厂商: Linear Technology
文件页数: 16/26页
文件大小: 0K
描述: IC REG CTRLR BST INV PWM 16TSSOP
标准包装: 95
PWM 型: 电流模式
输出数: 1
频率 - 最大: 225kHz
占空比: 100%
电源电压: 4 V ~ 60 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
LT3724
APPLICATIONS INFORMATION
The desired soft-start rise time (t SS ) is programmed via
a programming capacitor C SS1 , using a value that cor-
responds to 2μA average current during the soft-start
interval. This capacitor value follows the relation:
V OUT
C SS1 =
2 ? 10 –6 ? t SS
V OUT
V OUT(SS)
V(V C )
R SS is typically set to 200k for most applications.
TIME, 250μs/DIV
3724 F05
R SS =
? L ?
? C OUT ? ?
ConsiderationsforLow-VoltageOutputApplications
The LT3724 C SS pin biases to 220mV during the soft-start
cycle, and this voltage is increased at Figure 4 node “A” by
the 2μA signal current through R SS , so the output has to
reach this value before the soft-start function is engaged.
The value of this output soft-start startup voltage offset
(V OUT(SS) ) follows the relation:
V OUT(SS) = 220mV + R SS ? 2 ? 10 – 6
Which is typically 0.64V for R SS = 200k.
In some low voltage output applications, it may be desir-
able to reduce the value of this soft-start startup voltage
offset. This is possible by reducing the value of R SS . With
reduced values of R SS , the signal component caused by
voltage ripple on the output must be minimized for proper
soft-start operation.
Peak-to-peak output voltage ripple (?V OUT ) will be imposed
on node “A” through the capacitor C SS1 . The value of R SS
can be set using the following equation:
? V OUT
1.3 ? 10 – 6
It is important to use low ESR output capacitors for LT3724
voltage converter designs to minimize this ripple voltage
component. A design with an excessive ripple component
can be evidenced by observing the V C pin during the start
cycle.
The soft-start cycle should be evaluated to verify that the
reduced R SS value allows operation without excessive
modulation of the V C pin before finalizing the design.
If V C pin has an excessive ripple component during the
soft-start cycle, converter output ripple should be reduced.
Figure 5. Soft-Start Characteristic
Showing Excessive Ripple Component
V OUT
V OUT(SS)
V(V C )
TIME, 250μs/DIV
3724F06
Figure 6. Desirable Soft-Start Characteristic
This is typically accomplished by increasing output capaci-
tance and/or reducing output capacitor ESR.
External Current Limit Foldback Circuit
An additional startup voltage offset can occur during the
period before the LT3724 soft-start circuit becomes ac-
tive. Before the soft-start circuit throttles back the V C pin
in response to the rising output voltage, current as high
as the peak programmed current limit (I MAX ) can flow in
the switched inductor. Switching will stop once the soft-
start circuit takes hold and reduces the voltage on the
V C pin, but the output voltage will continue to increase
as the stored energy in the inductor is transferred to the
output capacitor. With I MAX in the inductor, the resulting
leading-edge rise on V OUT due to energy stored in the
inductor follows the relation:
1/2
? V OUT = I MAX ? ?
3724fd
16
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