参数资料
型号: LT3724IFE#PBF
厂商: Linear Technology
文件页数: 17/26页
文件大小: 0K
描述: IC REG CTRLR BST INV PWM 16TSSOP
标准包装: 95
PWM 型: 电流模式
输出数: 1
频率 - 最大: 225kHz
占空比: 100%
电源电压: 4 V ~ 60 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
LT3724
APPLICATIONS INFORMATION
Inductor current typically does not reach I MAX in the few
cycles that occur before soft-start becomes active, but can
with high input voltages or small inductors, so the above
relation is useful as a worst-case scenario.
V C
1N4148
1N4148
V OUT
Thisenergytransferincreaseinoutputvoltageistypically
small, but for some low voltage applications with relatively
small output capacitors, it can become significant. The volt-
age rise can be reduced by increasing output capacitance,
which puts additional limitations on C OUT for these low
voltage supplies. Another approach is to add an external
current limit foldback circuit which reduces the value of
I MAX during start-up.
An external current limit foldback circuit can be easily
incorporated into an LT3724 DC/DC converter application
by placing a 1N4148 diode and a 47kΩ resistor from the
converter output (V OUT ) to the LT3724’s V C pin. This limits
the peak current to 0.25 ? I MAX when V OUT = 0V. A cur-
rent limit foldback circuit also has the added advantage of
providing reduced output current in the DC/DC converter
during short-circuit fault conditions, so a foldback circuit
may be useful even if the soft-start function is disabled.
If the soft-start circuit is disabled by shorting the C SS pin
to ground, the external current limit foldback circuit must
be modified by adding an additional diode and resistor.
The 2-diode, 2-resistor network shown also provides 0.25
? I MAX when V OUT = 0V.
V C
1N4148
47k
3724 F03
Figure 7. Current Limit Foldback Circuit
for Applications that use Soft-Start
39k 27k
V OUT
3724 F07
Figure 8. Current Limit Foldback Circuit for Applications
that have Soft-Start Disabled (C SS Pin Shorted to SGND)
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. Express
percent efficiency as:
% Efficiency = 100% - (L1 + L2 + L3 + ...)
where L1, L2, etc. are individual loss terms as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main contributors usually account for most
of the losses in LT3724 circuits:
1. LT3724 V IN and V CC current loss
2. I 2 R conduction losses
3. MOSFET transition loss
4. Schottky diode conduction loss
1. The V IN and V CC currents are the sum of the quiescent
currents of the LT3724 and the MOSFET drive currents.
The quiescent currents are in the LT3724 Electrical Char-
acteristics table. The MOSFET drive current is a result
of charging the gate capacitance of the power MOSFET
each cycle with a packet of charge, Q G . Q G is found in
the MOSFET data sheet. The average charging current is
calculated as Q G ? f SW . The power loss term due to these
currents can be reduced by backdriving V CC with a lower
voltage than V IN such as V OUT .
3724fd
17
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