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参数资料
| 型号： | LT3825EFE#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 11/32页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBK ISO 16-TSSOP |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 250kHz |
| 占空比： | 88% |
| 电源电压： | 11 V ~ 18 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 带卷 (TR) |
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LT3825
OPERATION
R S(OUT) =
thatdevelopedundertheseconditions,forcedcontinuous
operation normally occurs. See Applications Information
for further details.
Enable Delay (ENDLY)
The flyback pulse appears when the primary-side switch
shuts off. However, it takes a finite time until the trans-
former primary-side voltage waveform represents the
output voltage. This is partly due to rise time on the
primary-side MOSFET drain node but, more importantly,
is due to transformer leakage inductance. The latter causes
a voltage spike on the primary side, not directly related
to output voltage. Some time is also required for internal
settling of the feedback amplifier circuitry. In order to
maintain immunity to these phenomena, a fixed delay is
introduced between the switch turn-off command and the
enabling of the feedback amplifier. This is termed “enable
delay.” In certain cases where the leakage spike is not
sufficiently settled by the end of the enable delay period,
regulation error may result. See Applications Information
for further details.
Collapse Detect
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the flyback
voltage (FB referred) to a fixed reference, nominally 80%
of V FB . When the flyback waveform drops below this level,
the feedback amplifier is disabled.
Minimum Enable Time
The feedback amplifier, once enabled, stays enabled for
a fixed minimum time period termed “minimum enable
time.” This prevents lockup, especially when the output
voltage is abnormally low; e.g., during start-up. The mini-
mum enable time period ensures that the V C node is able
to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. This time is set internally.
Effects of Variable Enable Period
The feedback amplifier is enabled during only a portion of
the cycle time. This can vary from the fixed minimum enable
time described to a maximum of roughly the “off” switch
time minus the enable delay time. Certain parameters of
feedback amp behavior are directly affected by the variable
enable period. These include effective transconductance
and V C node slew rate.
Load Compensation Theory
The LT3825 uses the flyback pulse to obtain information
about the isolated output voltage. An error source is
caused by transformer secondary current flow through
the synchronous MOSFET R DS(ON) and real life nonzero
impedances of the transformer secondary and output
capacitor. This was represented previously by the expres-
sion “I SEC ? ( ESR + R DS(ON) ).” However, it is generally
more useful to convert this expression to effective output
impedance. Because the secondary current only flows
during the off portion of the duty cycle (DC), the effective
output impedance equals the lumped secondary imped-
ance divided by OFF time DC.
Since the OFF time duty cycle is equal to 1 – DC then:
ESR + R DS(ON)
1 – DC
where:
R S(OUT) = effective supply output impedance
DC = duty cycle
R DS(ON) and ESR are as defined previously
This impedance error may be judged acceptable in less
critical applications, or if the output load current remains
relatively constant. In these cases the external FB resistive
divider is adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error is minimized by the use of the load compensation
function.
Figure 1 shows the Block Diagram of the load compensation
function. Switch current is converted to a voltage by the
external sense resistor, averaged and lowpass filtered by
the internal 50k resistor R CMPF and the external capacitor
on C CMP . This voltage is impressed across the external
R CMP resistor by op amp A1 and transistor Q3 producing a
current at the collector of Q3 that is subtracted from the FB
3825fe
11
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| LT383 | 制造商:EDSYN 功能描述: |
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| LT3837EFE#PBF | 功能描述:IC REG CTRLR FLYBK ISO 16-TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 特色产品:LM3753/54 Scalable 2-Phase Synchronous Buck Controllers 标准包装:1 系列:PowerWise® PWM 型:电压模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.5 V ~ 18 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-5°C ~ 125°C 封装/外壳:32-WFQFN 裸露焊盘 包装:Digi-Reel® 产品目录页面:1303 (CN2011-ZH PDF) 其它名称:LM3754SQDKR |
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