参数资料
型号: LT3825EFE#TRPBF
厂商: Linear Technology
文件页数: 25/32页
文件大小: 0K
描述: IC REG CTRLR FLYBK ISO 16-TSSOP
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 250kHz
占空比: 88%
电源电压: 11 V ~ 18 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 带卷 (TR)
LT3825
APPLICATIONS INFORMATION
C OUT ≥
5V ? ( 1 – 49% )
ESR COUT ≤ 1% ? = 3m ?
C OUT ≥
= 800 μ F
Theother1%isduetothebulkCcomponent,souse:
I OUT
1% ? V OUT ? f OSC
In many applications the output capacitor is created from
multiple capacitors to achieve desired voltage ripple, reli-
ability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satisfies the required bulk C.
Continuing our example, the output capacitor needs:
8A
8A
1% ? 5 ? 200kHz
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
Most capacitor ripple current ratings are based on 2000
hour life. This makes it advisable to derate the capacitor
or to choose a capacitor rated at a higher temperature
than required.
One way to reduce cost and improve output ripple is to use
a simple LC filter. Figure 8 shows an example of the filter.
The design of the filter is beyond the scope of this data
sheet. However, as a starting point, use these general
guide lines. Start with a C OUT 1/4 the size of the nonfilter
solution. Make C1 1/4 of C OUT to make the second filter
pole independent of C OUT . C1 may be best implemented
with multiple ceramic capacitors. Make L1 smaller than
the output inductance of the transformer. In general, a
0.1μH filter inductor is sufficient. Add a small ceramic
capacitor (C OUT2 ) for high frequency noise on V OUT . For
those interested in more details refer to “Second-Stage
LC Filter Design,” Ridley, Switching Power Magazine, July
2000, p8-10.
Circuit simulation is a way to optimize output capacitance
and filters, just make sure to include the component parasit-
ics. LTC SwitcherCAD ? is a terrific free circuit simulation
tool that is available at www.linear.com. Final optimization
of output ripple must be done on a dedicated PC board.
Parasitic inductance due to poor layout can significantly
impact ripple. Refer to the PC Board Layout section for
more details.
IC Thermal Considerations
Take care to ensure that the LT3825 junction temperature
does not exceed 125°C. Power is computed from the aver-
age supply current, the sum of quiescent supply current
(I CC in the specifications) plus gate drive currents.
The primary gate drive current is computed as:
f OSC ? Q G
where Q G is the total gate charge at max V GS (obtained from
the gate charge curve) and f is the switching frequency.
Since the synchronous driver is usually driving a capaci-
tive load, the synchronous gate drive power dissipation is:
f OSC ? C S ? V SGMAX
where C S is the SG capacitive load and V SGMAX is the SG
pin max voltage.
The total IC dissipation is computed as:
P D(TOTAL) = V CC ? ( I CC + f OSC ? ( Q GPRI + C S ? V SGMAX ))
V CC is the worst-case LT3825 supply voltage.
Junction temperature is computed as:
T J = T A + P D ? θ JA
where:
L1
0.1μH
V OUT
T A is the ambient temperature
FROM
SECONDARY
WINDING
C1
47μF
× 3
C OUT
470μF
C OUT2
1μF
3825 F08
R LOAD
θ JA is the FE16 package junction-to-ambient thermal
impedance (40°C/W).
Figure 8
3825fe
25
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