参数资料
| 型号： | LT8415IDDB#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC REG BOOST ADJ 25MA 12DFN |
| 标准包装： | 2,500 |
| 类型： | 升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 2.5 V ~ 40 V |
| 输入电压： | 2.5 V ~ 16 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 800kHz |
| 电流 - 输出： | 25mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 12-DFN-EP（3x2） |
LT8415
APPLICATIONS INFORMATION
If the application doesn’t require the output disconnect
function, the CAP and V OUT pin can be shorted, and higher
power converter ef?ciency can be achieved.
SHDN Pin Comparator and Hysteresis Current
An internal comparator compares the SHDN pin voltage
with an internal voltage reference (~1.3V) which gives a
precise turn-on voltage level. The internal hysteresis of this
turn-on voltage is about 60mV. When the chip is turned on,
and the SHDN pin voltage is close to this turn-on voltage,
0.1μA current ?ows out of the SHDN pin. This current is
called SHDN pin hysteresis current, and will go away when
the chip is off. By connecting the external resistors as in
Figure 2, a user-programmable enable voltage function
Board Layout Considerations
As with all switching regulators, careful attention must
be paid to the PCB layout and component placement. To
maximize ef?ciency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signal of the SW pin
has sharp rising and falling edges. Minimize the length and
area of all traces connected to the SW pin and always use
a ground plane under the switching regulator to minimize
interplane coupling. In addition, the FBP pin and V REF pin
are sensitive to noise. Minimizing the length and area of all
traces to these two pins is recommended. Recommended
component placement is shown in Figure 3.
can be realized.
The turn-on voltage for the con?guration is:
1.30 ? (1 + R1/R2)
V IN
SHDN
and the turn-off voltage is:
(1.24 – R3 ? 10 –7 ) ? (1 + R1/R2) – R1 ? 10 –7
where R1, R2 and R3 are resistance value in Ω.
SHDN
V CC
GND
SW
GND
FBP
V REF
CAP
V OUT
ENABLE VOLTAGE
IN1
OUT1
R1
R3
CONNECT TO
IN2
OUT2
SHDN PIN
8410 F03
R2
IN2
IN1
OUT1
OUT2
VIAS TO GROUND PLANE REQUIRED
TO IMPROVE THERMAL PERFORMANCE
Figure 2. Programming Enable Voltage by Using External
Resistors
Half-Bridge Control Signals
VIAS FOR CAP AND VOUT GROUND RETURN THROUGH
SECOND METAL LAYER, CAPACITOR GROUNDS MUST
BE RETURNED DIRECTLY TO IC GROUND
Figure 3. Recommended Board Layout
The half-bridge is controlled by the IN1 and IN2 pins. The
IN1 and IN2 pins should be driven with a logic signal.
When the chip is enabled, the OUT1 and OUT2 voltages
are equal to V OUT IN1 and IN2 are driven higher than 1V,
and they are near GND when IN1 and IN2 are driven below
0.3V. Do not drive the IN1 or IN2 pins between 0.3V to
1V for more than 20μs since this will leave OUT1 or OUT2
in an uncertain state and may also cause shoot-through
current.
8415f
10
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