参数资料
型号: LT8582EDKD#TRPBF
厂商: Linear Technology
文件页数: 23/36页
文件大小: 0K
描述: IC REG MULTI CONFIG ADJ 3A 24DFN
标准包装: 2,500
类型: 升压(升压),反相,回扫,Sepic
输出类型: 可调式
输出数: 2
输出电压: 最高 42V
输入电压: 2.5 V ~ 22 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 2.5MHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 24-DFN(7x4)

LT8582
APPENDIX
INDEPENDENT CHANNELS
Either channel may be used independently of the other
channel. To disable one channel, drive SHDN of that channel
low. Activating or deactivating one channel will not alter
the functionality of the other channel.
SETTING THE OUTPUT VOLTAGE
Duty cycle equations for several common topologies are
given below where V D is the diode forward voltage drop
and V CESAT is the collector to emitter saturation voltage
of the switch. V CESAT , with SWA and SWB tied together, is
typically 270mV when the combined switch current (I SWA
+ I SWB ) is 2.75A.
For the boost topology (see Figure 5):
The output voltage is set by connecting a resistor (R FBX )
from V OUT to the FBX pin. R FBX is determined by using
the following equation:
DC BOOST ?
V OUT – V IN + V D
V OUT + V D – V CESAT
R FBX =
DC SEPIC _& _ INVERT ?
| V OUT – V FBX |
83.3μA
where V FBX is 1.204V (typical) for noninverting topologies
(i.e. boost and SEPIC regulators) and 7mV (typical) for
inverting topologies (see the Electrical Characteristics).
For the SEPIC or dual inductor inverting topology (see
Figure 6 and Figure 7):
| V OUT | + V D
V IN + | V OUT | + V D – V CESAT
For the single inductor inverting topology (see Figure 12):
POWER SWITCH DUTY CYCLE
In order to maintain loop stability and deliver adequate
DC SI _ INVERT ?
| V OUT | –V IN + V CESAT + 3 ? V D
| V OUT | + 3 ? V D
current to the load, the power NPNs (Q1 and Q2 in the
Block Diagram) cannot remain on for 100% of each clock
cycle. The maximum allowable duty cycle is given by:
The LT8582 can be used in configurations where the duty
cycle is higher than DC MAX , but it must be operated in the
discontinuous conduction mode so that the effective duty
DC MA X =
(T P – MinOffTime)
T P
? 100%
cycle is reduced.
INDUCTOR SELECTION
DC MIN =
whereT P istheclockperiodandMinOffTime(foundinthe
Electrical Characteristics) is typically 45ns.
Conversely, the power NPNs (Q1 and Q2 in the Block
Diagram) cannot remain off for 100% of each clock cycle
and will turn on for a minimum on time (MinOnTime) when
in regulation. This MinOnTime governs the minimum al-
lowable duty cycle given by:
MinOnTime
? 100%
T P
Where T P is the clock period and MinOnTime (found in
the Electrical Characteristics) is typically 55ns.
The application should be designed such that the operating
duty cycle is between DC MIN and DC MAX .
General Guidelines
The high frequency operation of the LT8582 allows for the
use of small surface mount inductors. For high efficiency,
choose inductors with high frequency core material,
such as ferrite, to reduce core losses. Also to improve
efficiency, choose inductors with more volume for a given
inductance. The inductor should have low DCR (copper-
wire resistance) to reduce I 2 R losses and must be able to
handle the peak inductor current without saturating. Note
that in some applications, the current handling require-
ments of the inductor can be lower, such as in the SEPIC
topology where each inductor only carries one half of the
total switch current. Multilayer chip inductors usually do
not have enough core volume to support peak inductor
currents in the 2A to 6A range. To minimize radiated noise,
8582f
23
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