参数资料
型号: LTC1159IS-5#TR
厂商: Linear Technology
文件页数: 6/20页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16-SOIC
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 250kHz
占空比: 100%
电源电压: 4 V ~ 40 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
其它名称: LTC1159IS-5TR
LTC1159IS5TR
LTC1159
LTC1159-3.3/LTC1159-5
FU CTIO AL DIAGRA
Internal divider broken at V FB for adjustable versions.
V IN
V CC
P-GATE
SHDN2
EXTV CC
LOW DROPOUT
4.5V REGULATOR
LOW DROP SWITCH
CAP
V CC
550k
550k
P-DRIVE
N-GATE
R
V
PGND
SENSE +
SENSE –
SLEEP
Q
S
V TH1
C
25mV TO 150mV
V OS
+
T
13k
G
100k
S
V TH2
1.25V
V FB
LTC1159 ? FD
OFF-TIME
CONTROL
SENSE –
SGND
REFERENCE
SHDN1
C T
I TH
OPERATIO
(Refer to Functional Diagram)
The LTC1159 uses a current mode, constant off-time
architecture to synchronously switch an external pair of
complementary power MOSFETs. Operating frequency is
set by an external capacitor at the C T pin.
The output voltage is sensed either by an internal voltage
divider connected to the SENSE – pin (LTC1159-3.3 and
LTC1159-5) or an external divider returned to the V FB pin
(LTC1159). A voltage comparator V, and a gain block G,
compare the divided output voltage with a reference volt-
age of 1.25V. To optimize efficiency, the LTC1159 auto-
matically switches between two modes of operation, burst
and continuous.
A low dropout 4.5V regulator provides the operating volt-
age V CC for the MOSFET drivers and control circuitry during
start-up. During normal operation, the LTC1159 family
powers the drivers and control from the output via the
EXTV CC pin to improve efficiency. The N-GATE pin is
referenced to ground and drives the N-channel MOSFET
gate directly. The P-channel gate drive must be referenced
to the main supply input V IN , which is accomplished by
6
level-shifting the P-drive signal via an internal 550k resistor
and external capacitor.
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between the SENSE +
and SENSE – pins connected across an external shunt in
series with the inductor. When the voltage across the shunt
reaches its threshold value, the P-gate output is switched
to V IN , turning off the P-channel MOSFET. The timing
capacitor C T is now allowed to discharge at a rate deter-
mined by the off-time controller. The discharge current is
made proportional to the output voltage to model the
inductor current, which decays at a rate which is also
proportional to the output voltage. While the timing
capacitor is discharging, the N-gate output is high, turning
on the N-channel MOSFET.
When the voltage on C T has discharged past V TH1 , compara-
tor T trips, setting the flip-flop. This causes the N-gate output
to go low (turning off the N-channel MOSFET) and the P-
gate output to also go low (turning the P-channel MOSFET
back on). The cycle then repeats. As the load current
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