参数资料
型号: LTC1287CCN8#PBF
厂商: Linear Technology
文件页数: 3/16页
文件大小: 0K
描述: IC DATA ACQ SYS 12BIT 3V 8-DIP
标准包装: 50
类型: 数据采集系统(DAS)
分辨率(位): 12 b
采样率(每秒): 30k
数据接口: 串行,并联
电压电源: 单电源
电源电压: 3V
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
LTC1287
11
1287fa
DOUT
CLK
B11
HI-Z
B10
LTC1287 F8c
CS
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
tWHCS
tSMPL
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT
(–) INPUT
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Figure 9. Adequate Settling of Op Amp Driving Analog Input
(see Figures 8a, 8b and 8c). Again the “+” and “–” input
sampling times can be extended as described above to
accommodate slower op amps. For single supply low
voltage application the LT1797 and LT1677 can be made
to settle well even with the minimum settling windows of
6
s (“+” input) and 2s (“–” input) which occur at the
maximum clock rates (CLK = 500kHz). Figures 9 and 10
show examples of adequate and poor op amp settling. The
LT1077, LT1078 or LT1079 can be used here to reduce
power consumption. Placing an RC network at the output
of the op amps will inprove the settling response and also
reduce the broadband noise.
effectively “held” by the sample and hold and will not affect
the conversion result. It is critical that the “–” input voltage
be free of noise and settle completely during the first CLK
cycle of the conversion. Minimizing RSOURCE– and C2 will
improve settling time. If large “–” input source resistance
must be used the time can be extended by using a slower
CLK frequency. At the maximum CLK frequency of 500kHz,
RSOURCE– < 200 and C2 < 20pF will provide adequate
settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settles within the allowed time
HORIZONTAL: 500ns/DIV
Figure 8c. Setup Time (tSUCS) is Not Met
VERTICAL:
5mV/DIV
VERTICAL:
5mV/DIV
HORIZONTAL: 20
s/DIV
Figure 10. Poor Op Amp Settling Can Cause A/D Errors
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