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参数资料
| 型号： | LTC1325CSW |
| 厂商： | Linear Technology |
| 文件页数： | 14/24页 |
| 文件大小： | 0K |
| 描述： | IC BATTERY MANAGMNT SYSTEM18SOIC |
| 标准包装： | 40 |
| 功能： | 充电管理 |
| 电池化学： | 铅酸，锂离子，镍镉，镍氢 |
| 电源电压： | 4.5 V ~ 16 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 18-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 18-SOIC |
| 包装： | 管件 |
| 其它名称： | LTC1325CS |
LTC1325
FU N CTIO N AL DESCRIPTIO
V DD
4.5V TO 16V
CHARGE
DR0 TO
DR2
3
DUTY RATIO
GENERATOR
DISCHARGE
PGATE
DIS
P1
IRF9Z30
D1
R TRK
111kHz
OSCILLATOR
L1
1N5818
R DIS
ONE SHOT
GG
S1
R1
500k
R2
125k
R F
1k
BATTERY
SENSE
N1
IRFZ34
Q
S
+
C1
16pF
S2
S4
FILTER
C F
R SENSE
R
A2
–
S3
TO
ADC MUX
GG VR1 VR0 DAC VOLTAGE
A1
REG
3.072V
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
18mV
34mV
55mV
160mV
0mV
V DAC
DAC
2
VR0, VR1
GG
CHIP
(GAS GAUGE) BOUNDARY
Figure 4. Charging Loop Block Diagram
LTC1325 ? F04
rise as does the voltage across the sense resistor. When
the voltage across the sense resistor is greater than the
output of the integrator, comparator A2 changes state.
This resets the flip-flop and P1 is turned off. Catch diode
D1 clamps the drain of P1 one diode drop below ground
when the inductor flies back and the current through the
inductor starts to drop. The voltage across the sense
resistor also drops and may reach zero and stay there until
the next clock cycle begins.
The average charging current is set by the output of the
DAC (V DAC ) and the duty ratio generator. V DAC can be
programmed to one of four values with the following
ratios: 1, 1/3, 1/5 or 1/10. The duty ratio can be set to
1/16, 1/8, 1/4, 1/2 or 1. When the duty ratio is 1, the duty
ratio generator output is always low and the charge loop
operates continuously (see Figure 4). At other duty ratio
settings, the duty generator output is a square wave with
a period of 42 seconds. The time for which the generator
output is low varies with the duty ratio setting. For ex-
14
ample, if a duty ratio of 1/2 is programmed, the generator
output is low only for 42/2 = 21 seconds. Since the loop
operates for only 21 out of every 42 seconds, the average
charging current is halved. In general, the average charg-
ing current is:
I CHRG = V DAC (Duty Ratio)/R SENSE
Gated PFET Controller
When using an external current regulator or current lim-
ited wall pack, simply remove the inductor L1 and catch
diode D1. Set the DAC control bits VR1 = 1 and VR0 = 1,
and select the desired duty ratio. By insuring that the
voltage at the Sense pin is never greater than 140mV, the
output of the integrator A1 will saturate high and the
comparator A2 will never trip and turn the loop off. This
can be achieved by removing the sense resistor and
grounding the Sense pin or if the gas gauge is to be used,
selecting R SENSE so that R SENSE /I CHRG < 140mV.
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