参数资料
型号: LTC1408CUH#PBF
厂商: Linear Technology
文件页数: 10/20页
文件大小: 0K
描述: IC ADC 14BIT 600KSPS 32-QFN
标准包装: 73
位数: 14
采样率(每秒): 600k
数据接口: 串行
转换器数目: 1
功率耗散(最大): 15mW
电压电源: 模拟和数字
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 管件
输入数目和类型: 12 个单端,单极;12 个单端,双极;6 个差分,单极;6 个差分,双极
产品目录页面: 1346 (CN2011-ZH PDF)
配用: DC887A-ND - BOARD SAR ADC LTC1408
18
LTC1408
1408fa
APPLICATIO S I FOR ATIO
WU
UU
1408 F06
3
30
32
1
2
3-WIRE SERIAL
INTERFACE LINK
OVDD
CONV
SCK
LTC1408
SDO
VCC
BFSR
BCLKR
TMS320C54x
BDR
OGND
31
DGND
CONV
0V TO 3V LOGIC SWING
CLK
5V
3V
B13
B12
Figure 7. DSP Serial Interface to TMS320C54x
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC1408, a printed circuit board
with ground plane is required. Layout for the printed circuit
board should ensure that digital and analog signal lines are
separated as much as possible. In particular, care should
be taken not to run any digital track alongside an analog
signal track. If optimum phase match between the inputs
is desired, the length of the twelve input wires of the six
input channels should be kept matched. But each pair of
input wires to the six input channels should be kept
separated by a ground trace to avoid high frequency
crosstalk between channels.
High quality tantalum and ceramic bypass capacitors should
be used at the VCC, VDD and VREF pins as shown in the Block
Diagram on the first page of this data sheet. For optimum
performance, a 10
F surface mount tantalum capacitor
with a 0.1
F ceramic is recommended for the VCC,VDD and
VREF pins. Alternatively, 10F ceramic chip capacitors such
as X5R or X7R may be used. The capacitors must be lo-
cated as close to the pins as possible. The traces connect-
ing the pins and the bypass capacitors must be kept short
and should be made as wide as possible. The VCC and VDD
bypass capacitor returns to the ground plane and the VREF
bypass capacitor returns to the Pin 22. Care should be
taken to place the 0.1
F VCC and VDD bypass capacitor as
close to Pins 24 and 25 as possible.
Figure 6. Recommended Layout
Figure 6 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated at
the LTC1408 Exposed Pad. The ground return from the
LTC1408 to the power supply should be low impedance for
noise-free operation. The Exposed Pad of the 32-pin QFN
package is also internally tied to the ground pads. The
Exposed Pad should be soldered on the PC board to reduce
ground connection inductance. All ground pins (GND,
DGND, OGND) must be connected directly to the same
ground plane under the LTC1408.
VDD BYPASS,
0.1
F, 0402
OVDD BYPASS,
0.1
F, 0402
VREF BYPASS,
10
F, 0805
VCC BYPASS,
0.1
F, 0402 AND
10
F, 0805
HARDWARE INTERFACE TO TMS320C54x
The LTC1408 is a serial output ADC whose interface has
been designed for high speed buffered serial ports in fast
digital signal processors (DSPs). Figure 7 shows an
example of this interface using a TMS320C54X.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial data
can be collected in two alternating 1kB segments, in real
time, at the full 600ksps conversion rate of the LTC1408.
The DSP assembly code sets frame sync mode at the BFSR
pin to accept an external positive going pulse and the serial
clock at the BCLKR pin to accept an external positive edge
clock. Buffers near the LTC1408 may be added to drive
long tracks to the DSP to prevent corruption of the signal
to LTC1408. This configuration is adequate to traverse a
typical system board, but source resistors at the buffer
outputs and termination resistors at the DSP, may be
needed to match the characteristic impedance of very long
transmission lines. If you need to terminate the SDO
transmission line, buffer it first with one or two 74ACxx
gates. The TTL threshold inputs of the DSP port respond
properly to the 3V swing used with the LTC1408.
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