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| 型号： | LTC1408CUH#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 600KSPS 32-QFN |
| 标准包装： | 73 |
| 位数： | 14 |
| 采样率（每秒）： | 600k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 15mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
| 输入数目和类型： | 12 个单端，单极；12 个单端，双极；6 个差分，单极；6 个差分，双极 |
| 产品目录页面： | 1346 (CN2011-ZH PDF) |
| 配用： | DC887A-ND - BOARD SAR ADC LTC1408 |
17
LTC1408
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APPLICATIO S I FOR ATIO
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Minimizing Jitter on the CONV Input
In high speed applications where high amplitude sinewaves
above 100kHz are sampled, the CONV signal must have as
little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement easily. The challenge is to generate a
CONV signal from this crystal clock without jitter corrup-
tion from other digital circuits in the system. A clock
divider and any gates in the signal path from the crystal
clock to the CONV input should not share the same
integrated circuit with other parts of the system. The SCK
and CONV inputs should be driven first, with digital buffers
used to drive the serial port interface. Also note that the
master clock in the DSP may already be corrupted with
jitter, even if it comes directly from the DSP crystal.
Another problem with high speed processor clocks is that
they often use a low cost, low speed crystal (i.e., 10MHz)
to generate a fast, but jittery, phase-locked-loop system
clock (i.e., 40MHz). The jitter in these PLL-generated high
speed clocks can be several nanoseconds. Note that if you
choose to use the frame sync signal generated by the DSP
port, this signal will have the same jitter of the DSP’s
master clock.
The Typical Application Figure on page 20 shows a circuit
for level-shifting and squaring the output from an RF
signal generator or other low-jitter source. A single D-type
flip flop is used to generate the CONV signal to the
LTC1408. Re-timing the master clock signal eliminates
clock jitter introduced by the controlling device (DSP,
FPGA, etc.) Both the inverter and flip flop must be treated
as analog components and should be powered from a
clean analog supply.
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK sends out up to
six sets of 14 data bits, with the MSB sent first. A simple
approach is to generate SCK to drive the LTC1408 first and
then buffer this signal with the appropriate number of
inverters to drive the serial clock input of the processor
serial port. Use the falling edge of the clock to latch data
from the Serial Data Output (SDO) into your processor
serial port. The 14-bit Serial Data will be received right
justified, in six 16-bit words with 96 or more clocks per
frame sync. If fewer than 6 channels are selected by
SEL0–SEL2 for conversion, then 16 clocks are needed per
channel to convert the analog inputs and read out the
resulting data after the next convert pulse. It is good
practice to drive the LTC1408 SCK input first to avoid
digital noise interference during the internal bit compari-
son decision by the internal high speed comparator.
Unlike the CONV input, the SCK input is not sensitive to
jitter because the input signal is already sampled and held
constant.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset
to the high impedance state. The SDO output remains
in high impedance until a new conversion is started.
SDO sends out up to six sets of 14 bits in the output data
stream after the third rising edge of SCK after the start
of conversion with the rising edge of CONV. The six or
fewer 14-bit words are separated by two clock cycles in
high impedance mode. Please note the delay specifica-
tion from SCK to a valid SDO. SDO is always guaranteed
to be valid by the next rising edge of SCK. The 16 – 96-
bit output data stream is compatible with the 16-bit or
32-bit serial port of most processors.
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