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参数资料
| 型号： | LTC1408CUH#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 19/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 600KSPS 32-QFN |
| 标准包装： | 73 |
| 位数： | 14 |
| 采样率（每秒）： | 600k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 15mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
| 输入数目和类型： | 12 个单端，单极；12 个单端，双极；6 个差分，单极；6 个差分，双极 |
| 产品目录页面： | 1346 (CN2011-ZH PDF) |
| 配用： | DC887A-ND - BOARD SAR ADC LTC1408 |
8
LTC1408
1408fa
CH3+ (Pin 14): Non-Inverting Channel 3. CH3+ operates
fully differentially with respect to CH3– with a 0V to 2.5V,
or
±1.25V differential swing and a 0V to VDD absolute
input range.
CH3– (Pin 15): Inverting Channel 3. CH3– operates fully
differentially with respect to CH3+ with a –2.5V to 0V, or
±1.25V differential swing and a 0V to VDD absolute
input range.
CH4+ (Pin 17): Non-Inverting Channel 4. CH4+ operates
fully differentially with respect to CH4– with a 0V to 2.5V,
or
±1.25V differential swing and a 0V to VDD absolute input
range.
CH4– (Pin 18): Inverting Channel 4. CH4– operates fully
differentially with respect to CH4+ with a –2.5V to 0V, or
±1.25V differential swing and a 0V to VDD absolute input
range.
CH5+ (Pin 20): Non-Inverting Channel 5. CH5+ operates
fully differentially with respect to CH5– with a 0V to 2.5V,
or
±1.25V differential swing and a 0V to VDD absolute input
range.
CH5– (Pin 21): Inverting Channel 5. CH5– operates fully
differentially with respect to CH5+ with a –2.5V to 0V, or
±1.25V differential swing and a 0V to VDD absolute input
range.
GND (PIN 22): Analog Ground for Reference. Analog
ground must be tied directly to the solid ground plane
under the part. Analog signal currents flow through this
connection. The 10
F reference bypass capacitor should
be returned to this pad.
VREF (Pin 23): 2.5V Internal Reference. Bypass to GND
and a solid analog ground plane with a 10
F ceramic
capacitor (or 10
F tantalum in parallel with 0.1F ce-
ramic). Can be overdriven by an external reference voltage
between 2.55% and VDD, VCC.
VCC (Pin 24): 3V Positive Analog Supply. This pin supplies
3V to the analog section. Bypass to the solid analog
ground plane with a 10
F ceramic capacitor (or 10F
tantalum) in parallel with 0.1
F ceramic. Care should be
taken to place the 0.1
F bypass capacitor as close to
Pin 24 as possible. Pin 24 must be tied to Pin 25.
VDD (Pin 25): 3V Positive Digital Supply. This pin supplies
3V to the logic section. Bypass to DGND pin and solid
analog ground plane with a 10
F ceramic capacitor (or
10
F tantalum in parallel with 0.1F ceramic). Keep in
mind that internal digital output signal currents flow
through this pin. Care should be taken to place the 0.1
F
bypass capacitor as close to Pin 25 as possible. Pin 25
must be tied to Pin 24.
SEL2 (Pin 26): Most significant bit controlling the
number of channels being converted. In combination with
SEL1 and SEL0, 000 selects just the first channel (CH0) for
conversion. Incrementing SELx selects additional
channels(CH0–CH5) for conversion. 101, 110 or 111
select all 6 channels for conversion. Must be kept in a fixed
state during conversion and during the subsequent con-
version to read data.
SEL1 (Pin 27): Middle significance bit controlling the
number of channels being converted. In combination with
SEL0 and SEL2, 000 selects just the first channel (CH0) for
conversion. Incrementing SELx selects additional
channels for conversion. 101, 110 or 111 select all 6
channels (CH0–CH5) for conversion. Must be kept in a
fixed state during conversion and during the subsequent
conversion to read data.
SEL0 (Pin 28): Least significant bit controlling the
number of channels being converted. In combination with
SEL1 and SEL2, 000 selects just the first channel (CH0) for
conversion. Incrementing SELx selects additional
channels for conversion. 101, 110 or 111 select all 6
channels (CH0–CH5) for conversion. Must be kept in a
fixed state during conversion and during the subsequent
conversion to read data.
BIP (Pin 29): Bipolar/Unipolar Mode. The input differen-
tial range is 0V – 2.5V when BIP is LOW, and it is
±1.25
when BIP is HIGH. Must be kept in fixed state during
conversion and during subsequent conversion to read
data. When changing BIP between conversions the full
acquisition time must be allowed before starting the next
conversion. The output data is in 2’s complement
format for bipolar mode and straight binary format for
unipolar mode.
UU
U
PI FU CTIO S
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