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参数资料
| 型号： | LTC1649CS#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 16-SOIC |
| 标准包装： | 50 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 260kHz |
| 占空比： | 93% |
| 电源电压： | 2.7 V ~ 5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
LTC1649
APPLICATIO N S I N FOR M ATIO N
resume normal operation. The CP OUT pin remains regu-
lated at 5V in shutdown, and can be used as a keep-alive
supply for external circuitry if desired. Note that any
An easy way to simplify the math is to choose
R2 = 12.65k ? . This simplifies the equation to:
current drawn from the CP OUT pin adds to the quiescent
current in shutdown, and subtracts from the current
V OUT =
R 1
10k ?
+ 1.265V
available to drive the external MOSFETs if the load remains
connected while the LTC1649 is active.
External Clock Synchronization
The LTC1649 SHDN pin can double as an external clock
input for applications that require a synchronized clock or
a faster switching speed. The SHDN pin terminates the
internal sawtooth wave and resets the oscillator immedi-
ately when it goes low, but waits 50 μ s before shutting
down the rest of the internal circuitry. A clock signal
applied directly to the SHDN pin will force the LTC1649
internal oscillator to lock to its frequency as long as the
external clock runs faster than the internal oscillator
A typical 2.5V output application might use R1 = 12.35k ? ,
R2 = 12.65k ? . The nearest standard 1% values are
R1 = 12.4k ? , R2 = 12.7k ? , which gives an output voltage
of 2.5001V—pretty close to 2.5V.
Note that using 1% resistors can cause as much as 1%
error in the output voltage in a typical LTC1649 applica-
tion—a significant fraction of the total output error. 0.1%
or 0.25% feedback resistors are recommended for appli-
cations which require the output voltage to be controlled
to better than 3%.
V OUT
R1
frequency. The LTC1649 can be synchronized to frequen-
cies between 250kHz and about 350kHz.
LTC1649
FB
R2
+
C OUT
Frequencies above 350kHz can cause erratic current limit
GND
operation and are not recommended.
1659 F08
Setting the Output Voltage
The LTC1649 feedback loop senses the output voltage at
the FB pin. The loop regulates FB to 1.265V; to set the
output voltage, FB should be connected to the output node
through a resistor divider, set up so the voltage at FB is
1.265V when the output is at the desired voltage (see
Figure 8). The upper end of R1 should be connected to the
output voltage as close to the load as possible, to minimize
errors caused by resistance in the output leads. The
bottom of R2 should be connected to the high power
ground node, at the GND pin of the LTC1649.
R1 and R2 should be chosen so that:
Figure 8. Resistor Divider at FB Pin
LAYOUT CONSIDERATIONS
Grounding
Proper grounding is critical for the LTC1649 to obtain
specified output regulation. Extremely high peak currents
(as high as several amps) can flow between the bypass
capacitors and the PV CC1 , PV CC2 and GND pins. These
currents can generate significant voltage differences be-
tween two points that are nominally both “ground.” As a
general rule, power and signal grounds should be totally
V OUT =
R 1 + R 2
R2
V REF =
R 1 + R 2
R2
(1.265V)
separated on the layout, and should be brought together
at only one point, right at the LTC1649 GND pin. This helps
minimize internal ground disturbances in the LTC1649,
while preventing excessive current flow from disrupting
the operation of the circuits connected to GND. The high
power GND node should be as compact and low imped-
ance as possible, with the negative terminals of the input
13
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