参数资料
型号: LTC1735IS#PBF
厂商: Linear Technology
文件页数: 14/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16-SOIC
标准包装: 50
PWM 型: 电流模式
输出数: 1
频率 - 最大: 335kHz
占空比: 99.4%
电源电压: 4 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 管件
产品目录页面: 1333 (CN2011-ZH PDF)
LTC1735
APPLICATIO S I FOR ATIO
C IN Selection
In continuous mode, the source current of the top
N-channel MOSFET is a square wave of duty cycle V OUT /
V IN . To prevent large voltage transients, a low ESR input
capacitor sized for the maximum RMS current must be
used. The maximum RMS capacitor current is given by:
The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran-
tees that the output capacitance does not significantly
discharge during the operating frequency period due to
ripple current. The choice of using smaller output capaci-
tance increases the ripple voltage due to the discharging
term but can be compensated for by using capacitors of
V ? V IN
I RMS O ( MAX ) OUT ?
– 1 ?
? I
V IN ? V OUT
?
?
1 / 2
very low ESR to maintain the ripple voltage at or below
50mV. The I TH pin OPTI-LOOP compensation compo-
nents can be optimized to provide stable, high perfor-
mance transient response regardless of the output capaci-
This formula has a maximum at V IN = 2V OUT , where
I RMS = I O(MAX) /2. This simple worst case condition is com-
monly used for design because even significant deviations do
not offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours of
life. This makes it advisable to further derate the capacitor or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
size or height requirements in the design. Always consult the
manufacturer if there is any question.
C OUT Selection
The selection of C OUT is primarily determined by the
effective series resistance (ESR) to minimize voltage
ripple. The output ripple ( ? V OUT ) in continuous mode is
determined by:
tors selected.
The selection of output capacitors for CPU or other appli-
cations with large load current transients is primarily
determined by the voltage tolerance specifications of the
load. The resistive component of the capacitor, ESR,
multiplied by the load current change plus any output
voltage ripple must be within the voltage tolerance of the
load (CPU).
The required ESR due to a load current step is:
R ESR < ? V/ ? I
where ? I is the change in current from full load to zero load
(or minimum load) and ? V is the allowed voltage deviation
(not including any droop due to finite capacitance).
The amount of capacitance needed is determined by the
? V OUT ≈ ? I L ? ESR +
8 fC OUT ?
?
?
1 ?
?
maximum energy stored in the inductor. The capacitance
must be sufficient to absorb the change in inductor current
when a high current to low current transition occurs. The
opposite load current transition is generally determined by
C OUT >
Where f = operating frequency, C OUT = output capaci-
tance and ? I L = ripple current in the inductor. The output
ripple is highest at maximum input voltage since ? I L
increases with input voltage. Typically, once the ESR
requirement for C OUT has been met, the RMS current
rating generally far exceeds the I RIPPLE(P–P) requirement.
With ? I L = 0.3I OUT(MAX) and allowing 2/3 of the ripple due
to ESR the output ripple will be less than 50mV at max V IN
assuming:
C OUT required ESR < 2.2 R SENSE
C OUT > 1/(8fR SENSE )
the control loop OPTI-LOOP components, so make sure
not to over compensate and slow down the response. The
minimum capacitance to assure the inductors’ energy is
adequately absorbed is:
L ( ? I ) 2
2 ( ? V ) V OUT
where ? I is the change in load current.
Manufacturers such as Nichicon, United Chemi-Con and
Sanyo can be considered for high performance through-
hole capacitors. The OS-CON semiconductor electrolyte
1735fc
14
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