参数资料
| 型号： | LTC1736IG#TR |
| 厂商： | Linear Technology |
| 文件页数： | 20/28页 |
| 文件大小： | 0K |
| 描述： | IC REG SW SYNC STEPDWN HE 24SSOP |
| 标准包装： | 1,800 |
| 应用： | 转换器，Intel Pentium? II，III |
| 输入电压： | 3.5 V ~ 36 V |
| 输出数： | 1 |
| 输出电压： | 0.93 V ~ 2 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 24-SSOP |
| 包装： | 带卷 (TR) |
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LTC1736
APPLICATIO S I FOR ATIO
In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.17 μ A
internal current source pulling the pin high. Remember to
include this current when choosing resistor values R3 and
R4.
The internal LTC1736 oscillator can be synchronized to an
external oscillator by clocking the FCB pin with a signal
above 1.5V P-P . When synchronized to an external fre-
quency, Burst Mode operation is disabled, but cycle skip-
ping is allowed at low load currents since current reversal
is inhibited. The bottom gate will come on every 10 clock
cycles to assure the boostrap cap, C B , is kept refreshed.
The rising edge of an external clock applied to the FCB pin
starts a new cycle.
The range of synchronization is from 0.9f O to 1.3f O , with
f O set by C OSC . Attempting to synchronize to a higher
frequency than 1.3f O can result in inadequate slope
comensation and cause loop instability with high duty
cycles. If loop instability is observed while synchronized,
additional slope compensation can be obtained by simply
decreasing C OSC .
The following table summarizes the possible states avail-
able on the FCB pin:
Table 2
where L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1736 circuits: 1) LTC1736 V IN current, 2)
INTV CC current, 3) I 2 R losses, 4) Topside MOSFET transi-
tion losses.
1. The V IN current is the DC supply current given in the
electrical characteristics which excludes MOSFET driver
and control currents. V IN current results in a small
(< 0.1%) loss that increases with V IN .
2. INTV CC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTV CC to ground. The resulting dQ/dt is a current
out of INTV CC that is typically much larger than the
control circuit current. In continuous mode, I GATECHG =
f(Q T + Q B ), where Q T and Q B are the gate charges of the
topside and bottom-side MOSFETs.
Supplying INTV CC power through the EXTV CC switch
input from an output-derived or other high efficiency
source will scale the V IN current required for the driver
FCB Pin
DC Voltage: 0V to 0.7V
DC Voltage: > 0.9V
Feedback Resistors
Condition
Burst Disabled/Forced Continuous
Current Reversal Enabled
Burst Mode Operation, No Current Reversal
Regulating a Secondary Winding
and control circuits by a factor of (Duty Cycle)/(Effi-
ciency). For example, in a 15V to 1.8V application, 10mA
of INTV CC current results in approximately 1.2mA of V IN
current. This reduces the low current loss from 10% or
more (if the driver was powered directly from V IN ) to only
Ext Clock: (0V to V FCBSYNC ) Burst Mode Operation Disabled
(V FCBSYNC ≥ 1.5V) No Current Reversal
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% - (L1 + L2 + L3 + ...)
20
a few percent.
3. I 2 R Losses are predicted from the DC resistances of the
MOSFETs, inductor and current shunt. In continuous
mode the average output current flows through L and
R SENSE , but is “chopped” between the topside main
MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same R DS(ON) , then
the resistance of one MOSFET can simply be summed
with the resistances of L and R SENSE to obtain I 2 R
losses. For example, if each R DS(ON) = 0.02 ? , R L =
0.03 ? , and R SENSE = 0.01 ? , then the total resistance is
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