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| 型号： | LTC1753CSW#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 13/24页 |
| 文件大小： | 0K |
| 描述： | IC SW REG CNTRLR PENT III 20SOIC |
| 标准包装： | 38 |
| 应用： | 控制器，Intel Pentium? III |
| 输入电压： | 5V |
| 输出数： | 1 |
| 输出电压： | 1.3 V ~ 3.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC |
| 包装： | 管件 |
LTC1753
APPLICATIO S I FOR ATIO
mounted next to the external MOSFET which is expected
to run the hottest –– often the high-side device, Q1. Elec-
trically, the thermistor should form a voltage divider with
another resistor, R1, connected to V CC . Their midpoint
should be connected to OUTEN (see Figure 6). As the
temperature increases, the OUTEN pin voltage is reduced.
Under normal operating conditions, the OUTEN pin should
stay above 1.7V and all circuits will function normally. If
the temperature gets abnormally high, the OUTEN pin
voltage will eventually drop below 1.7V, the LTC1753
disables both FET drivers. If OUTEN decreases below
1.2V, the LTC1753 enters shutdown mode. To activate any
of these three modes, the OUTEN voltage must drop below
the respective threshold for longer than 30 μ s.
V IN
MOSFET Gate Drive
Power for the internal MOSFET drivers is supplied by
PV CC . This supply must be above the input supply voltage
by at least one power MOSFET V GS(ON) for efficient
operation. For a typical application, PV CC should be con-
nected to a 12V power supply.
If the OUTEN pin is low, G1 and G2 are both held low to
prevent output voltage undershoot. As V CC and PV CC
power up from a 0V condition, an internal undervoltage
lockout circuit prevents G1 and G2 from going high until
V CC reaches about 3.5V. If V CC powers up while PV CC is at
ground potential, the SS is forced to ground potential
internally. SS clamps the COMP pin low and prevents the
drivers from turning on. On power-up or recovery from
thermal shutdown, the drivers are designed such that G2
V CC
R1
LTC1753
G1
Q1
L O
+
V OUT
is held low until G1 first goes high.
Power MOSFETs
R2
NTC THERMISTOR
OUTEN
G2
Q2
C OUT
Two N-channel power MOSFETs are required for most
MOUNT IN CLOSE
THERMAL PROXIMITY
LTC1753 circuits. Logic level MOSFETs should be used
TO Q1
1753 F06
and they should be selected based on on-resistance and
Figure 6. OUTEN Pin as a Thermistor Input
Clock Synchronization
The internal oscillator can be synchronized to an external
clock by applying the external clocking signal to the
OUTEN pin. The synchronizing range extends from the
initial operating frequency up to 500kHz. If the external
frequency is much higher than the natural free-running
frequency, the peak-to-peak sawtooth amplitude within
the LTC1753 will decrease. Since the loop gain is inversely
proportional to the amplitude of the sawtooth, the com-
pensation network may need to be adjusted slightly. Note
that the temperature sensing circuitry does not operate
GATE threshold voltage considerations. R DS(ON) should
be chosen based on input and output voltage, allowable
power dissipation and maximum required output current.
GATE threshold voltages for logic level MOSFETs are
lower than standard MOSFETs. A MOSFET whose R DS(ON)
is rated at V GS = 4.5V does not necessarily have a logic
level MOSFET GATE threshold voltage. Using standard
MOSFETs instead of logic level MOSFETs can cause start-
up problems, especially if PV CC is derived from a charge
pump scheme. In a typical LTC1753 buck converter circuit
the average inductor current is equal to the output load
current. This current is always flowing through either Q1
or Q2 with the power dissipation split up according to the
duty cycle:
( )
DC Q 1 = OUT
( )
DC Q 2 = 1 ? =
when external synchronization is used.
V
V IN
V OUT
V IN
(
V IN ? V OUT
V IN
)
1753fa
13
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