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| 型号： | LTC1753CSW#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/24页 |
| 文件大小： | 0K |
| 描述： | IC SW REG CNTRLR PENT III 20SOIC |
| 标准包装： | 38 |
| 应用： | 控制器，Intel Pentium? III |
| 输入电压： | 5V |
| 输出数： | 1 |
| 输出电压： | 1.3 V ~ 3.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC |
| 包装： | 管件 |
LTC1753
APPLICATIO S I FOR ATIO
Note that capacitor manufacturers’ ripple current ratings
are often based on only 2000 hours (three months)
lifetime at rated temperature. Further derating of the input
capacitor ripple current beyond the manufacturer’s speci-
fication is recommended to extend the useful life of the
circuit. Lower operating temperature will have the largest
effect on capacitor longevity.
The output capacitor in a buck converter sees much less
ripple current under steady-state conditions than the input
capacitor. Peak-to-peak current is equal to that in the
inductor, usually 10% to 40% of the total load current.
Output capacitor duty places a premium not on power
dissipation but on ESR. During an output load transient,
the output capacitor must supply all of the additional load
current demanded by the load until the LTC1753 can
adjust the inductor current to the new value. Output
capacitor ESR results in a step in the output voltage equal
to the ESR value multiplied by the change in load current.
An 11A load step with a 0.05 ? ESR output capacitor will
result in a 550mV output voltage shift; this is 19.6% of the
output voltage for a 2.8V supply! Because of the strong
feature 2.3A allowable ripple current at 85 ° C; three in
parallel at the input (to withstand the input ripple current)
will meet the above requirements. Similarly, AVX
TPSE337M006R0100 (330 μ F/6V) have a rated maximum
ESR of 0.1 ? ; seven in parallel will lower the net output
capacitor ESR to 0.014 ? . For low cost application, Sanyo
MV-GX series of capacitors can be used with acceptable
performance. The small size, low profile Sanyo OS-CON
4SP820M comes with extremely low ESR (typically 0.008 ?
at room temperature). This is an excellent choice for
output capacitor usage. However, due to the low ESR, it
requires attention to frequency compensation. Refer to
the Feedback Loop Compensation section for details.
Feedback Loop Compensation
The LTC1753 voltage feedback loop is compensated at the
COMP pin, attached to the output node of the internal g m
error amplifier. The feedback loop can generally be com-
pensated properly with an RC + C network from COMP to
GND as shown in Figure 7a.
relationship between output capacitor ESR and output
load transient response, the output capacitor is usually
1 μ F
6 SENSE
chosen for ESR, not for capacitance value; a capacitor with
suitable ESR will usually have a larger capacitance value
than is needed for energy storage.
Electrolytic capacitors rated for use in switching power
COMP
10
LTC1753
ERR
R2
R1
V FB
11
C2
supplies with specified ripple current ratings and ESR can
be used effectively in LTC1753 applications. OS-CON
electrolytic capacitors from Sanyo and other manufactur-
ers give excellent performance and have a very high
R C
C C
C1
DAC
performance/size ratio for electrolytic capacitors. Surface
mount applications can use either electrolytic or dry
f LC =
tantalum capacitors. Tantalum capacitors must be surge
tested and specified for use in switching power supplies.
Low cost, generic tantalums are known to have very short
lives followed by explosive deaths in switching power
supply applications. AVX TPS series surface mount
devices are popular surge tested tantalum capacitors that
work well in LTC1753 applications.
A common way to lower ESR and raise ripple current
capability is to parallel several capacitors. A typical LTC1753
application might exhibit 5A input ripple current. Sanyo
OS-CON part number 10SA220M (220 μ F/10V) capacitors
1753 F07a
Figure 7a. Compensation Pin Hook-Up
Loop stability is affected by the values of the inductor,
output capacitor, output capacitor ESR, FET R DS(ON), error
amplifier transconductance and error amplifier compen-
sation network. The inductor and the output capacitor
create a double pole at the frequency:
1
2 π√ (L O )(C OUT )
1753fa
16
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