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| 型号： | LTC1753CSW#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 19/24页 |
| 文件大小： | 0K |
| 描述： | IC SW REG CNTRLR PENT III 20SOIC |
| 标准包装： | 38 |
| 应用： | 控制器，Intel Pentium? III |
| 输入电压： | 5V |
| 输出数： | 1 |
| 输出电压： | 1.3 V ~ 3.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC |
| 包装： | 管件 |
LTC1753
APPLICATIO S I FOR ATIO
possible. It should also be located as close as possible
above (or below) the power ground plane. Some of the
phase shift problem can be solved by taking the AC
feedback locally at the regulator output while still taking
the DC feedback at the point of load. This permits accurate
DC regulation while still maintaining reasonable phase
margin. This is done by connecting the top of phase lead
capacitor, C2, locally at the regulator output while con-
necting the SENSE pin to the load. The corner frequency
1/(2 π ? R2 ? C2) must be significantly less than the
resonant frequency of the parasitic inductance and the
output capacitance 1/(2 π ? √ L DIST ? C LOAD ). Certain board
layouts may require R C2 , a small series resistor, to de-
crease the slew rate of the feedforward path. In general, an
empirical approach to compensating this type of loop will
be best since it will be very difficult to estimate the parasitic
inductance of the power path analytically. It should be
noted that if the circuit can have a wide range of output
capacitance, this can be dangerous technique to employ
since the double-pole frequency will move as the load
capacitance changes. Be sure to verify stability with all
possible combinations of output capacitance.
VID0 to VID4, PWRGD and FAULT
The digital inputs (VID0 to VID4) program the internal DAC
which in turn controls the output voltage. These digital
input controls are intended to be static and are not
designed for high speed switching. Forcing V OUT to step
from a high to a low voltage by changing the VID n pins
quickly can cause FAULT to trip.
Figure 9 shows the relationship between the V OUT voltage,
PWRGD and FAULT. To prevent PWRGD from interrupting
the CPU unnecessarily, the LTC1753 has a built-in t PWRBAD
delay to prevent noise at the SENSE pin from toggling
PWRGD. The internal time delay is designed to take about
500 μ s for PWRGD to go low and 1ms for it to recover.
Once PWRGD goes low, the internal circuitry watches for
the output voltage to exceed 113% of the rated voltage. If
this happens, FAULT will be triggered. Once FAULT is
triggered, G1 and G2 will be forced low immediately and
the LTC1753 will remain in this state until V CC power
supply is recycled or OUTEN is toggled.
13%
V OUT
3%
Q1
L O
L DIST
RATED V OUT
Q2
+
C OUT
1 μ F
+
LOAD
– 3%
t PWRBAD
t PWRGD
t FAULT
6 SENSE
1 μ F
R C2
C LOAD
PWRGD
FAULT
COMP
LTC1753
R2
V FB
11
C2
Figure 9. PWRGD and FAULT
1753 F09
10
ERR
R1
R C
C C
C1
DAC
1753 F08
Figure 8. Feedback Connections for Remote Sense Applications
1753fa
19
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| LTC1754ES6-3.3#TR | 功能描述:IC REG SWITCHED CAP 3.3V SOT23-6 RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:500 系列:- 类型:切换式电容器（充电泵），反相 输出类型:固定 输出数:1 输出电压:-3V 输入电压:2.3 V ~ 5.5 V PWM 型:Burst Mode? 频率 - 开关:900kHz 电流 - 输出:100mA 同步整流器:无 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SOT-23-6 细型，TSOT-23-6 包装:带卷 (TR) 供应商设备封装:TSOT-23-6 其它名称:LTC1983ES6-3#TRMTR |
| LTC1754ES6-3.3#TRM | 功能描述:IC REG SWITCHED CAP 3.3V SOT23-6 RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:500 系列:- 类型:切换式电容器（充电泵），反相 输出类型:固定 输出数:1 输出电压:-3V 输入电压:2.3 V ~ 5.5 V PWM 型:Burst Mode? 频率 - 开关:900kHz 电流 - 输出:100mA 同步整流器:无 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SOT-23-6 细型，TSOT-23-6 包装:带卷 (TR) 供应商设备封装:TSOT-23-6 其它名称:LTC1983ES6-3#TRMTR |
| LTC1754ES6-3.3#TRMPBF | 功能描述:IC REG SWITCHED CAP 3.3V SOT23-6 RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:500 系列:- 类型:切换式电容器（充电泵），反相 输出类型:固定 输出数:1 输出电压:-3V 输入电压:2.3 V ~ 5.5 V PWM 型:Burst Mode? 频率 - 开关:900kHz 电流 - 输出:100mA 同步整流器:无 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:SOT-23-6 细型，TSOT-23-6 包装:带卷 (TR) 供应商设备封装:TSOT-23-6 其它名称:LTC1983ES6-3#TRMTR |
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