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| 型号： | LTC1753CSW#TR |
| 厂商： | Linear Technology |
| 文件页数： | 17/24页 |
| 文件大小： | 0K |
| 描述： | IC REG SW 5BIT PROG SYNC 20SOIC |
| 标准包装： | 1,000 |
| 应用： | 控制器，Intel Pentium? III |
| 输入电压： | 5V |
| 输出数： | 1 |
| 输出电压： | 1.3 V ~ 3.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC |
| 包装： | 带卷 (TR) |
LTC1753
APPLICATIO S I FOR ATIO
The ESR of the output capacitor forms a zero at the
frequency:
poor load transient response despite the improvement in
output voltage ripple.
f ESR =
1
2 π (ESR)(C OUT )
To resolve this problem, a small capacitor can be con-
nected between the SENSE and V FB pins to create a pole-
zero pair in the loop compensation. The zero location is
The compensation network at the error amplifier output is
to provide enough phase margin at the 0dB crossover
frequency for the overall closed-loop transfer function.
The zero and pole from the compensation network are:
prior to the pole location and thus, phase lead can be
added to boost the phase margin at the loop crossover
frequency. The pole and zero locations are located at:
f ZC2 =
and f PC2 =
f Z =
1
2 π (R C )(C C )
and f P =
1
2 π (R C )(C1)
respectively.
1 1
2 π (R2)(C2) 2 π (R12)(C2)
where R12 is the parallel combination resistance of R1 and
Figure 7b shows the Bode plot of the overall transfer
function.
The compensation value used in this design is based on
the following criteria: f SW = 12f CO , f Z = f LC and f P = 5f CO . At
the loop crossover frequency f CO , the attenuation due the
LC filter and the input resistor divider is compensated by
the gain of the PWM modulator and the gain of the error
amplifier (g mERR )(R C ).
When low ESR output capacitors (Sanyo OS-CON) are
used, the ESR zero can be high enough in frequency that
it provides little phase boost at the loop crossover fre-
quency. Therefore, inadequate phase margin is obtained
for the system. This causes loop stability problems and
f SW = LTC1753 SWITCHING
FREQUENCY
R2. Choose C2 so that the zero is located at a lower
frequency compared to f CO and the pole location is high
enough that the closed loop has enough phase margin for
stability. Figure 7c shows the Bode plot using phase lead
compensation around the LTC1753 internal resistor
divider network.
Although a mathematical approach to frequency compen-
sation can be used, the added complication of input and/
or output filters, unknown capacitor ESR, and gross
operating point changes with input voltage, load current
variations, all suggest a more practical empirical method.
This can be done by injecting a transient current at the load
and using an RC network box to iterate toward the final
compensation values, or by obtaining the optimum loop
f SW = LTC1753 SWITCHING
FREQUENCY
f Z
f CO = CLOSED-LOOP CROSSOVER
FREQUENCY
f CO = CLOSED-LOOP CROSSOVER
FREQUENCY
f Z
– 20dB/DECADE
– 20dB/DECADE
f CO
f P
f P f PC2
f LC
f ESR
f CO
FREQUENCY
f LC
f ZC2
FREQUENCY
f ESR
1753 F07b
Figure 7b. Bode Plot of the LTC1753 Overall Transfer Function
1753 F07c
Figure 7c. Bode Plot of the LTC1753 Overall Transfer Function
Using a Low ESR Output Capacitor
1753fa
17
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