参数资料
型号: LTC1876EG
厂商: Linear Technology
文件页数: 16/36页
文件大小: 0K
描述: IC REG CTRLR BST PWM CM 36-SSOP
标准包装: 37
系列: PolyPhase®
PWM 型: 电流模式
输出数: 3
频率 - 最大: 360kHz
占空比: 99.4%
电源电压: 3.5 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-SSOP(0.209",5.30mm 宽)
包装: 管件
LTC1876
APPLICATIO S I FOR ATIO
then, sub-logic level threshold MOSFETs (V GS(TH) < 3V)
should be used. Pay close attention to the BV DSS specifi-
cation for the MOSFETs as well; most of the logic level
MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance R DS(ON) , reverse transfer capacitance C RSS ,
input voltage and maximum output current. When the
LTC1876 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized R DS(ON) vs temperature curve, but
δ = 0.005/ ° C can be used as an approximation for low
voltage MOSFETs. C RSS is usually specified in the MOS-
FET characteristics. The constant k = 1.7 can be used to
estimate the contributions of the two terms in the main
switch dissipation equation.
The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
Main Switch Duty Cycle =
V OUT
V IN
MOSFET from turning on, storing charge during the dead-
time and requiring a reverse recovery period that could
cost as much as 3% in efficiency at high V IN . A 1A to 3A
Synchronous Switch Duty Cycle =
V IN – V OUT
V IN
Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance.
( ) ( 1 + δ ) R DS ( ON ) +
V OUT
P MAIN =
k ( V IN ) ( I MAX )( C RSS )( )
( ) ( 1 + δ ) R DS ( ON )
V IN – V OUT
P SYNC =
The  MOSFET  power  dissipations  at  maximum  output
current are given by:
2
I MAX
V IN
2
f
2
I MAX
V IN
where δ is the temperature dependency of R DS(ON) and k
is a constant inversely related to the gate drive current.
Both MOSFETs have I 2 R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V IN < 20V the
high current efficiency generally improves with larger
MOSFETs, while for V IN > 20V the transition losses rapidly
increase to the point that the use of a higher R DS(ON) device
with lower C RSS actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.
C IN Selection
The selection of C IN is simplified by the multiphase archi-
tecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
when only one controller is operating. The controller with
the highest (V OUT )(I OUT ) product needs to be used in the
formula below to determine the maximum RMS current
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease
the RMS ripple current from this maximum value (see
Figure 4). The out-of-phase technique typically reduces
the input capacitor’s RMS ripple current by a factor of 30%
to 70% when compared to a single phase power supply
solution.
The type of input capacitor, value and ESR rating have
efficiency effects that need to be considered in the selec-
tion process. The capacitance value chosen should be
sufficient to store adequate charge to keep high peak
battery currents down. 20 μ F to 40 μ F is usually sufficient
for a 25W output supply operating at 200kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery efficiency. All of the power (RMS
ripple current ? ESR) not only heats up the capacitor but
wastes power from the battery.
1876fa
16
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