参数资料
型号: LTC2206UK-14#TR
厂商: LINEAR TECHNOLOGY CORP
元件分类: ADC
英文描述: PROPRIETARY METHOD ADC, PQCC48
封装: 7 X 7 MM, PLASTIC, MO-220WKKD-2, QFN-48
文件页数: 1/32页
文件大小: 1307K
代理商: LTC2206UK-14#TR
LTC2207-14/LTC2206-14
1
220714614fa
FEATURES
DESCRIPTIO
U
TYPICAL APPLICATIO
U
APPLICATIO S
U
FREQUENCY (MHz)
0
AMPLITUDE
(dBFS)
–70
–30
0
40
22076 TA01b
–90
–110
–80
–50
–10
–20
–40
–60
–100
–120
10
20
30
50
14-Bit, 105Msps/80Msps
ADCs
The LTC2207-14/LTC2206-14 are 105Msps/80Msps,
sampling 14-bit A/D converters designed for digitizing
high frequency, wide dynamic range signals up to input
frequencies of 700MHz. The input range of the ADC can
be optimized with the PGA front end.
The LTC2207-14/LTC2206-14 are perfect for demanding
communications applications, with AC performance that
includes 77.3dB SNR and 98dB spurious free dynamic
range (SFDR). Ultralow jitter of 80fsRMS allows under-
sampling of high input frequencies with excellent noise
performance. Maximum DC specs include ±1.5LSB INL,
±1LSB DNL (no missing codes) over temperature.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC+ and ENCinputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
Sample Rate: 105Msps/80Msps
77.3dBFS Noise Floor
98dB SFDR
SFDR >82dB at 250MHz (1.5VP-P Input Range)
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
Single 3.3V Supply
Power Dissipation: 947mW/762mW
Optional Clock Duty Cycle Stabilizer
Out-of-Range Indicator
Pin Compatible Family
105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)
80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)
65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit)
40Msps: LTC2204 (16-Bit)
25Msps: LTC2203 (16-Bit) Single-Ended Clock
10Msps: LTC2202 (16-Bit) Single-Ended Clock
48-Pin 7mm
× 7mm QFN Package
+
S/H
AMP
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC CORE
INTERNAL ADC
REFERENCE
GENERATOR
1.25V
COMMON MODE
BIAS VOLTAGE
CLOCK/DUTY
CYCLE
CONTROL
D13
D0
ENC+
PGA
SHDN
DITH
MODE
OE
RAND
ENC
VCM
ANALOG
INPUT
22076 TA01
0.5V TO 3.6V
3.3V
SENSE
OGND
OVDD
2.2
F
0.1
F
0.1
F
0.1
F
0.1
F
VDD
GND
ADC CONTROL INPUTS
AIN+
AIN
OF
CLKOUT+
CLKOUT
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Patents Pending.
LTC2207-14: 32K Point FFT,
fIN = 14.86MHz, –1dBFS,
PGA = 0, 105Msps
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