参数资料
型号: LTC2206UK-14#TR
厂商: LINEAR TECHNOLOGY CORP
元件分类: ADC
英文描述: PROPRIETARY METHOD ADC, PQCC48
封装: 7 X 7 MM, PLASTIC, MO-220WKKD-2, QFN-48
文件页数: 7/32页
文件大小: 1307K
代理商: LTC2206UK-14#TR
LTC2207-14/LTC2206-14
15
220714614fa
OPERATION
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band lim-
ited to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the RMS
amplitude of all other frequency components, except the
rst ve harmonics.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = –20Log (
(V
2
2 + V32 + V42 + ... VN2)/V1)
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through nth harmonics.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 3rd order IMD terms include (2fa + fb),
DITH
OE
MODE
PGA RAND
SHDN
ADC CLOCKS
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
DITHER
SIGNAL
GENERATOR
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
ENC+
ENC
CORRECTION LOGIC
AND
SHIFT REGISTER
OGND
CLKOUT+
CLKOUT–
OF
D13
D12
OVDD
D1
D0
22076 F01
INPUT
S/H
AIN
AIN
+
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
VDD
GND
PGA
SENSE
VCM
BUFFER
ADC
REFERENCE
VOLTAGE
REFERENCE
RANGE
SELECT
Figure 1. Functional Block Diagram
BLOCK DIAGRAM
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