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| 型号： | LTC2208CUP#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 16-Bit, 130Msps ADC; Package: QFN; No of Pins: 64; Temperature Range: 0°C to +70°C |
| 中文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封装： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件页数： | 10/32页 |
| 文件大小： | 959K |
| 代理商： | LTC2208CUP#PBF |
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LTC2208
18
2208fc
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2208 CMOS
differential sample and hold. The differential analog inputs
are sampled directly onto sampling capacitors (CSAMPLE)
through NMOS transitors. The capacitors shown attached
to each input (CPARASITIC) are the summation of all other
capacitance associated with each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when ENC is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As ENC
transitions for high to low, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time. If the change
between the last sample and the new sample is small,
the charging glitch seen at the input will be small. If the
Figure 2. Equivalent Input Circuit
CSAMPLE
4.9pF
VDD
LTC2208
AIN+
2208 F02
CSAMPLE
4.9pF
VDD
AIN–
ENC–
ENC+
1.6V
6k
1.6V
6k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
APPLICATIONS INFORMATION
CONVERTER OPERATION
The LTC2208 is a CMOS pipelined multistep converter
with a front-end PGA. As shown in Figure 1, the converter
has ve pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles later (see the
Timing Diagrams section). The analog input is differen-
tial for improved common mode noise immunity and to
maximize the input range. Additionally, the differential
input drive will reduce even order harmonics of the sample
and hold circuit. The encode input is also differential for
improved common mode noise immunity.
The LTC2208 has two phases of operation, determined
by the state of the differential ENC+/ENC– input pins. For
brevity, the text will refer to ENC+ greater than ENC– as
ENC high and ENC+ less than ENC– as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplier. In op-
eration, the ADC quantizes the input to the stage and the
quantized value is subtracted from the input by the DAC
to produce a residue. The residue is amplied and output
by the residue amplier. Successive stages operate out
of phase so that when odd stages are outputting their
residue, the even stages are acquiring that residue and
vice versa.
When ENC is low, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that ENC transitions from low to high, the voltage
on the sample capacitors is held. While ENC is high, the
held input voltage is buffered by the S/H amplier which
drives the rst pipelined ADC stage. The rst stage acquires
the output of the S/H amplier during the high phase of
ENC. When ENC goes back low, the rst stage produces
its residue which is acquired by the second stage. At the
same time, the input S/H goes back to acquiring the analog
input. When ENC goes high, the second stage produces
its residue which is acquired by the third stage. An iden-
tical process is repeated for the third and fourth stages,
resulting in a fourth stage residue that is sent to the fth
stage for nal evaluation.
Each ADC stage following the rst has additional range to
accommodate ash and amplier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
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| LTC2208IUP | 制造商:Linear Technology 功能描述:ADC Single Pipelined 130Msps 16-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 130MSPS 64-QFN |
| LTC2208IUP#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 130Msps 16-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 130MSPS 64-QFN 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 130MSPS, QFN-64; Resolution (Bits):16bit; Sampling Rate:130MSPS; Supply Voltage Type:Single; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Supply Current:380mA; Digital IC Case Style:QFN; No. of Pins:64 ;RoHS Compliant: Yes |
| LTC2208IUP#TR | 制造商:Linear Technology 功能描述:IC ADC 16BIT 130MSPS 64-QFN |
| LTC2208IUP#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 130Msps 16-bit Parallel/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT 130MSPS 64-QFN |
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