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参数资料
| 型号： | LTC2208CUP#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 16-Bit, 130Msps ADC; Package: QFN; No of Pins: 64; Temperature Range: 0°C to +70°C |
| 中文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封装： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件页数： | 16/32页 |
| 文件大小： | 959K |
| 代理商： | LTC2208CUP#PBF |
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LTC2208
23
2208fc
resistor, even if the signal is not used (such as OF+/OF– or
CLKOUT+/CLKOUT–). To minimize noise the PC board
traces for each LVDS output pair should be routed close
together. To minimize clock skew all LVDS PC board traces
should have about the same length.
In Low Power LVDS Mode 1.75mA is steered between
the differential outputs, resulting in ±175mV at the LVDS
receiver’s 100
Ω termination resistor. The output com-
mon mode voltage is 1.20V, the same as standard LVDS
Mode.
Data Format
The LTC2208 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. This pin has a four level
logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An
external resistor divider can be user to set the 1/3VDD
and 2/3VDD logic levels. Table 2 shows the logic states
for the MODE pin.
Table 2. MODE Pin Function
MODE
OUTPUT FORMAT
CLOCK DUTY
CYCLE STABILIZER
0(GND)
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
LTC2208
2208 F11
OVDD
VDD
0.1μF
TYPICAL
DATA
OUTPUT
OGND
43Ω
OVDD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
Figure 11. Equivalent Circuit for a Digital Output Buffer
output may be used but is not required since the ADC has
a series resistor of 43
Ω on chip.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Digital Output Buffers (LVDS Modes)
Figure 12 shows an equivalent circuit for an LVDS output
pair. A 3.5mA current is steered from OUT+ to OUT– or
vice versa, which creates a ±350mV differential voltage
across the 100
Ω termination resistor at the LVDS receiver.
A feedback loop regulates the common mode output volt-
age to 1.20V. For proper operation each LVDS output pair
must be terminated with an external 100
Ω termination
LTC2208
2208 F12
3.5mA
1.20V
LVDS
RECEIVER
OGND
10k
VDD
0.1μF
OVDD
3.3V
PREDRIVER
LOGIC
DATA
FROM
LATCH
+
–
OVDD
43Ω
100Ω
Figure 12. Equivalent Output Buffer in LVDS Mode
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