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参数资料
| 型号： | LTC2208CUP#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 16-Bit, 130Msps ADC; Package: QFN; No of Pins: 64; Temperature Range: 0°C to +70°C |
| 中文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封装： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件页数： | 15/32页 |
| 文件大小： | 959K |
| 代理商： | LTC2208CUP#PBF |
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LTC2208
22
2208fc
The lower limit of the LTC2208 sample rate is determined
by droop of the sample and hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specied minimum operating frequency
for the LTC2208 is 1Msps.
DIGITAL OUTPUTS
Digital Output Modes
The LTC2208 can operate in four digital output modes:
standard LVDS, low power LVDS, full rate CMOS, and
demultiplexed CMOS. The LVDS pin selects the mode of
operation. This pin has a four level logic input, centered at
0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can
be used to set the 1/3VDD and 2/3VDD logic levels. Table 1
shows the logic states for the LVDS pin.
Table 1. LVDS Pin Function
LVDS
DIGITAL OUTPUT MODE
0V(GND)
Full-Rate CMOS
1/3VDD
Demultiplexed CMOS
2/3VDD
Low Power LVDS
VDD
LVDS
Digital Output Buffers (CMOS Modes)
Figure 11 shows an equivalent circuit for a single output
buffer in CMOS Mode, Full-Rate or Demultiplexed. Each
buffer is powered by OVDD and OGND, isolated from the
ADC power and ground. The additional N-channel transistor
in the output driver allows operation down to low voltages.
The internal resistor in series with the output makes the
output appear as 50
Ω to external circuitry and eliminates
the need for external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2208 should drive a minimum
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as a ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
2208 F10
ENC–
83Ω
130Ω
ENC+
3.3V
D0
Q0
MC100LVELT22
LTC2208
Figure 10. ENC Drive Using a CMOS to PECL Translator
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2208 is 130Msps.
For the ADC to operate properly the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have at
least 3.65ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS. When using a single-ended ENCODE
signal asymmetric rise and fall times can result in duty
cycles that are far from 50%.
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC pin to sample the analog input.
The falling edge of ENC is ignored and an internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3VDD or 2/3VDD using external resistors.
Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter
2208 F09
ENC–
1.6V
VTHRESHOLD = 1.6V
ENC+
0.1μF
LTC2208
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| LTC2208IUP | 制造商:Linear Technology 功能描述:ADC Single Pipelined 130Msps 16-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 130MSPS 64-QFN |
| LTC2208IUP#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 130Msps 16-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 130MSPS 64-QFN 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 130MSPS, QFN-64; Resolution (Bits):16bit; Sampling Rate:130MSPS; Supply Voltage Type:Single; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Supply Current:380mA; Digital IC Case Style:QFN; No. of Pins:64 ;RoHS Compliant: Yes |
| LTC2208IUP#TR | 制造商:Linear Technology 功能描述:IC ADC 16BIT 130MSPS 64-QFN |
| LTC2208IUP#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 130Msps 16-bit Parallel/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT 130MSPS 64-QFN |
| LTC2208IUP-14 | 制造商:Linear Technology 功能描述:IC ADC 14BIT 130MSPS 64-QFN |
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