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参数资料
| 型号： | LTC2285IUP#3CGPBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | PROPRIETARY METHOD ADC, PQCC64 |
| 封装： | 9 X 9 MM, LEAD FREE, PLASTIC, QFN-64 |
| 文件页数： | 8/24页 |
| 文件大小： | 578K |
| 代理商： | LTC2285IUP#3CGPBF |
LTC2285IUP#3CGPBF
16
2285iup#3cgpbf
APPLICATIONS INFORMATION
Figure 11. Sinusoidal Single-Ended CLK Drive
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
Figure 13. LVDS or PECL CLK Drive Using a Transformer
The noise performance of the LTC2285IUP#3CGPBF can
depend on the clock signal quality as much as on the analog
input. Any noise present on the clock signal will result in
additional aperture jitter that will be RMS summed with
the inherent ADC aperture jitter.
In applications where jitter is critical, such as when digi-
tizing high input frequencies, use as large an amplitude
as possible. Also, if the ADC is clocked with a sinusoidal
signal, lter the CLK signal to reduce wideband noise and
distortion products generated by the source.
It is recommended that CLKA and CLKB are shorted to-
gether and driven by the same clock source. If a small time
delay is desired between when the two channels sample
the analog inputs, CLKA and CLKB can be driven by two
different signals. If this delay exceeds 1ns, the performance
of the part may degrade. CLKA and CLKB should not be
driven by asynchronous signals.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use
of a transformer provides no incremental contribution
to phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz will
degrade the SNR compared to the transformer solution.
The nature of the received signals also has a large bear-
ing on how much SNR degradation will be experienced.
For high crest factor signals such as WCDMA or OFDM,
where the nominal power level must be at least 6dB to
8dB below full scale, the use of these translators will have
a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may be
desirable in cases where lower voltage differential signals
are considered. The center tap may be bypassed to ground
through a capacitor close to the ADC if the differential
signals originate on a different plane. The use of a ca-
pacitor at the input may result in peaking, and depending
on transmission line length may require a 10Ω to 20Ω
ohm series resistor to act as both a low pass lter for
high frequency noise that may be induced into the clock
line by neighboring digital signals, as well as a damping
mechanism for reections.
Maximum and Minimum Conversion Rates
ThemaximumconversionratefortheLTC2285IUP#3CGPBF
is 135Msps. The lower limit of the LTC2285IUP#3CGPBF
sample rate is determined by droop of the sample-and-hold
circuits. The pipelined architecture of this ADC relies on
CLK
50Ω
0.1μF
4.7μF
1k
FERRITE
BEAD
CLEAN
SUPPLY
SINUSOIDAL
CLOCK
INPUT
2285 F11
NC7SVU04
LTC2285IUP
#3CGPBF
CLK
100Ω
0.1μF
4.7μF
FERRITE
BEAD
CLEAN
SUPPLY
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
2285 F12
LTC2285IUP
#3CGPBF
CLK
5pF-30pF
ETC1-1T
0.1μF
VCM
FERRITE
BEAD
DIFFERENTIAL
CLOCK
INPUT
2285 F13
LTC2285IUP
#3CGPBF
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相关代理商/技术参数 |
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|---|---|
| LTC2285IUPPBF | 制造商:Linear Technology 功能描述:ADC, Dual 14b 125Msps, 3V, LTC2285IUP |
| LTC2285IUP-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 14-Bit, 125Msps Low Power 3V ADC |
| LTC2285IUP-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 14-Bit, 125Msps Low Power 3V ADC |
| LTC2285IUP-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 14-Bit, 125Msps Low Power 3V ADC |
| LTC2285UP | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 14-Bit, 135Msps Low Power 3.3V ADC |
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