参数资料
型号: LTC3547EDDB-1#TRPBF
厂商: Linear Technology
文件页数: 11/16页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ .3A DL 8DFN
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.6 V ~ 5.5 V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 2.25MHz
电流 - 输出: 300mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 8-DFN(3x2)
LTC3547
APPLICATIO S I FOR ATIO
Ef?ciency Considerations
The percent ef?ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the ef?ciency and which change would
produce the most improvement. Percent ef?ciency can
be expressed as:
% Ef?ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four sources usually account for the losses in
LTC3547 circuits: 1) V IN quiescent current, 2) switching
losses, 3) I 2 R losses, 4) other system losses.
1) The V IN current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET
driver and control currents. V IN current results in a
small (<0.1%) loss that increases with V IN , even at
no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from V IN to ground. The resulting dQ/dt is a current out
of V IN that is typically much larger than the DC bias cur-
rent. In continuous mode, I GATECHG = f O (Q T + Q B ), where
Q T and Q B are the gate charges of the internal top and
bottom MOSFET switches. The gate charge losses are
proportional to V IN and thus their effects will be more
pronounced at higher supply voltages.
3) I 2 R losses are calculated from the DC resistances of
the internal switches, R SW , and external inductor,
R L . In continuous mode, the average output current
?ows through inductor L, but is “chopped” between
the internal top and bottom switches. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R DS(ON) and the duty cycle
(DC) as follows:
R SW = (R DS(ON)TOP ) ? (DC) + (R DS(ON)BOT ) ? (1 – DC)
(5)
The R DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. Thus, to obtain I 2 R losses:
I 2 R losses = I OUT2 ? (R SW + R L )
4) Other “hidden” losses, such as copper trace and in-
ternal battery resistances, can account for additional
ef?ciency degradations in portable systems. It is very
important to include these “system” level losses in
the design of a system. The internal battery and fuse
resistance losses can be minimized by making sure that
C IN has adequate charge storage and very low ESR at
the switching frequency. Other losses, including diode
conduction losses during dead-time, and inductor
core losses, generally account for less than 2% total
additional loss.
3547fa
11
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