参数资料
型号: LTC3547EDDB-1#TRPBF
厂商: Linear Technology
文件页数: 12/16页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ .3A DL 8DFN
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.6 V ~ 5.5 V
输入电压: 2.5 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 2.25MHz
电流 - 输出: 300mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 8-DFN(3x2)
LTC3547
APPLICATIO S I FOR ATIO
Thermal Considerations
In a majority of applications, the LTC3547 does not dis-
sipate much heat due to its high ef?ciency. In the unlikely
event that the junction temperature somehow reaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
The goal of the following thermal analysis is to determine
whether the power dissipated causes enough temperature
rise to exceed the maximum junction temperature (125°C)
of the part. The temperature rise is given by:
T RISE = P D ? θ JA (6)
Where P D is the power dissipated by the regulator and
θ JA is the thermal resistance from the junction of the die
to the ambient temperature.
The junction temperature, T J , is given by:
T J = T RISE + T AMBIENT (7)
As a worst-case example, consider the case when the
LTC3547 is in dropout on both channels at an input volt-
age of 2.7V with a load current of 300mA and an ambi-
ent temperature of 70°C. From the Typical Performance
Characteristics graph of Switch Resistance, the R DS(ON)
of the main switch is 0.9 Ω . Therefore, power dissipated
by each channel is:
P D = I OUT2 ? R DS(ON) = 81mV
Given that the thermal resistance of a properly soldered
DFN package is approximately 76°C/W, the junction
temperature of an LTC3547 device operating in a 70°C
ambient temperature is approximately:
T J = (2 ? 0.081W ? 76°C/W) + 70°C = 82.3°C
which is well below the absolute maximum junction tem-
perature of 125°C.
PC Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3547. These items are also illustrated graphically
in the layout diagrams of Figures 2 and 3. Check the fol-
lowing in your layout:
1. Does the capacitor C IN connect to the power V IN (Pin 3)
and GND (Pin 5) as closely as possible? This capacitor
provides the AC current of the internal power MOSFETs
and their drivers.
2. Are the respective C OUT and L closely connected?
The (–) plate of C OUT returns current to GND and the
(–) plate of C IN .
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C OUT1 and a ground sense
line terminated near GND (Pin 5). The feedback sig-
nals V FB1 and V FB2 should be routed away from noisy
components and traces, such as the SW lines (Pins 4
and 6), and their trace length should be minimized.
4. Keep sensitive components away from the SW pins if
possible. The input capacitor C IN and the resistors R1,
R2, R3 and R4 should be routed away from the SW
traces and the inductors.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at a single
point. These ground traces should not share the high
current path of C IN or C OUT .
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. These copper areas should be
connected to V IN or GND.
3547fa
12
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