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| 型号： | LTC3548IMSE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ DL 10MSOP |
| 标准包装： | 50 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.6 V ~ 5 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 2.25MHz |
| 电流 - 输出： | 400mA，800mA |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 10-MSOP 裸露焊盘 |
LTC3548
APPLICATIONS INFORMATION
= 1.9μH
L ≥
4.2V ? ?
? ? 1–
Δ I L =
? ? 1 ?
= 204mA
Design Example
As a design example, consider using the LTC3548 in an
portable application with a Li-Ion battery. The battery pro-
vides a V IN = 2.8V to 4.2V. The load requires a maximum
of 800mA in active mode and 2mA in standby mode. The
output voltage is V OUT = 2.5V. Since the load still needs
power in standby, Burst Mode operation is selected for
good low load ef?ciency.
First, calculate the inductor value for about 30% ripple
current at maximum V IN :
2.5V ? 2.5V ?
2.25MHz ? 240mA ?
Choosing a vendor’s closest inductor value of 2.2μH,
results in a maximum ripple current of:
2.5V ? 2.5V ?
?
2.25MHz ? 2.2 μH ? 4.2V ?
For cost reasons, a ceramic capacitor will be used. C OUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3548. These items are also illustrated graphically
in the layout diagram of Figure 4. Check the following in
your layout:
1. Does the capacitor C IN connect to the power V IN (Pin
3) and GND (exposed pad) as close as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
2. Are the C OUT and L1 closely connected? The (–) plate
of C OUT returns current to GND and the (–) plate
of C IN .
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C OUT and a ground sense line
terminated near GND (exposed pad). The feedback sig-
nals V FB should be routed away from noisy components
and traces, such as the SW line (Pins 4 and 7), and its
trace should be minimized.
4. Keep sensitive components away from the SW pins.
C OUT ≈ 2.5
800mA
2.25MHz ? (5% ? 2.5V)
= 7.1μF
The input capacitor C IN and the resistors R1 to R4
should be routed away from the SW traces and the
inductors.
A good standard value is 10μF. Since the output impedance
of a Li-Ion battery is very low, C IN is typically 10μF.
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high ef?ciency, the
current in these resistors should be kept small. Choosing
2μA with the 0.6V feedback voltage makes R1~300k. A close
standard 1% resistor is 280k, and R2 is then 887k.
The POR pin is a common drain output and requires a pull-
up resistor. A 100k resistor is used for adequate speed.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at one
point and should not share the high current path of
C IN or C OUT .
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. These copper areas should be
connected to V IN or GND.
Figure 3 shows the complete schematic for this design
example.
3548fc
12
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