参数资料
型号: LTC3613IWKH#PBF
厂商: Linear Technology
文件页数: 4/36页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 15A 56QFN
标准包装: 40
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 5.5 V
输入电压: 4.5 V ~ 24 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 1MHz
电流 - 输出: 15A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 56-VFQFN 裸露焊盘
包装: 管件
供应商设备封装: 56-QFN 多焊盘(7x9)
LTC3613
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at T A = 25°C. SV IN = 15V, V FB = V OSNS+ – V OSNS– , unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator and Clock Synchronization
f OSC
Free Running Switching Frequency
R T = 205k
R T = 80.6k
R T = 38.8k
175
450
900
200
500
1000
225
550
1100
kHz
kHz
kHz
CLK IH
CLK IL
Clock Input High Level Into Mode/PLLIN
Clock Input Low Level Into Mode/PLLIN
2
0.5
V
V
Internal V CC Regulator and External V CC
INTV CC
INTV CC(%)
EXTV CC(TH)
Internal V CC Voltage
Internal V CC Load Regulation
EXTV CC Switchover Voltage
6V < V IN < 24V
I CC = 0mA to 50mA
EXTV CC Rising
5.1
4.4
5.3
–1
4.6
5.55
–2
4.75
V
%
V
EXTV CC(HYS)
EXTV CC Switchover Hysteresis
200
mV
ΔINTV CC
EXTV CC Voltage Drop
V EXTVCC = 5V. I CC = 50mA
200
mV
PGOOD Output
PGD OV
PGOOD Upper Threshold
V FB Rising (With Respect to Regulated
5
7.5
10
%
Feedback Voltage V REG )
PGD UV
PGOOD Lower Threshold
V FB Falling (With Respect to Regulated
–10
–7.5
–5
%
Feedback Voltage V REG )
PGD HYS
PGOOD Hysteresis
V FB Returning
2
%
V PGD(LO)
t PGD(FALL)
PGOOD Low Voltage
Delay from OV/UV Fault to PGOOD Falling
I PGOOD = 5mA
(Note 5)
0.15
20
0.4
V
μs
t PGD(RISE)
Delay from OV/UV Recovery to PGOOD Rising (Note 5)
10
μs
R DS(ON)
R DS(ON)
Top Switch On-Resistance
Bottom Switch On-Resistance
7.5
5.5
mohm
mohm
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: T J is calculated from the ambient temperature, T A , and power
dissipation, P D , as follows:
T J = T A + (P D ? 29°C/W) ( θ JA is simulated per JESD51-7 high effective
thermal conductivity test board)
θ JC =1°C/W ( θ JC is simulated when heat sink is applied at the bottom
of the package.)
Note 3: The LTC3613 is tested in a feedback loop that adjusts V FB = V OSNS+
– V OSNS– to achieve a specified error amplifier output voltage (ITH).
Note 4: The LTC3613 is tested under pulsed load conditions such that
T J ≈ T A . The LTC3613E is guaranteed to meet specifications from
0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3613I is guaranteed over the full –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 5: Delay times are measured using 50% levels.
3613fa
4
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