参数资料
型号: LTC3707IGN#TRPBF
厂商: Linear Technology
文件页数: 15/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 28-SSOP
标准包装: 2,500
系列: PolyPhase®
PWM 型: 电流模式
输出数: 2
频率 - 最大: 360kHz
占空比: 99.4%
电源电压: 4.5 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 28-SSOP(0.154",3.90mm 宽)
包装: 带卷 (TR)
LTC3707
APPLICATIONS INFORMATION
Main Switch Duty Cycle =
However, designs for surface mount are available that do
not increase the height signi?cantly.
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for each
controller with the LTC3707: One N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTV CC
voltage. This voltage is typically 5V during start-up
(see EXTV CC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(V IN < 5V); then, sub-logic level threshold MOSFETs
(V GS(TH) < 3V) should be used. Pay close attention to the
BV DSS speci?cation for the MOSFETs as well; most of the
logic level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance R DS(ON) , reverse transfer capacitance C RSS , input
voltage and maximum output current. When the LTC3707
is operating in continuous mode the duty cycles for the
top and bottom MOSFETs are given by:
V OUT
V IN
which are highest at high input voltages. For V IN < 20V
the high current ef?ciency generally improves with larger
MOSFETs, while for V IN > 20V the transition losses rapidly
increase to the point that the use of a higher R DS(ON) device
with lower C RSS actually provides higher ef?ciency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1+ δ ) is generally given for a MOSFET in the
form of a normalized R DS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. C RSS is usually speci?ed in the MOSFET
characteristics. The constant k = 1.7 can be used to esti-
mate the contributions of the two terms in the main switch
dissipation equation.
The Schottky diode D1 shown in Figure 1 conducts dur-
ing the dead-time between the conduction of the two
power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead-time and requiring a reverse recovery period
that could cost as much as 3% in ef?ciency at high V IN .
A 1A to 3A Schottky is generally a good compromise for
both regions of operation due to the relatively small aver-
age current. Larger diodes result in additional transition
Synchronous Switch Duty Cycle =
V IN – V OUT
V IN
losses due to their larger junction capacitance. Schottky
diodes should be placed in parallel with the synchronous
MOSFETs when operating in pulse-skip mode or in Burst
The MOSFET power dissipations at maximum output
current are given by:
Mode operation.
C IN and C OUT Selection
P MAIN =
V OUT
V IN
( I MAX ) 2 ( 1 + δ ) R DS(ON) +
The selection of C IN is simpli?ed by the multiphase ar-
chitecture and its impact on the worst-case RMS current
k ( V IN ) ( I MAX ) ( C RSS ) ( f )
2
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
P SYNC =
V IN – V OUT
V IN
( I MAX ) 2 ( 1 + δ ) R DS(ON)
when only one controller is operating. The controller with
the highest (V OUT )(I OUT ) product needs to be used in the
formula below to determine the maximum RMS current
where δ is the temperature dependency of R DS(ON) and k
is a constant inversely related to the gate drive current.
Both MOSFETs have I 2 R losses while the topside N-channel
equation includes an additional term for transition losses,
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease the
input RMS ripple current from this maximum value (see
Figure 4). The out-of-phase technique typically reduces
the input capacitor’s RMS ripple current by a factor of
3707fb
15
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