参数资料
型号: LTC3708EUH#TRPBF
厂商: Linear Technology
文件页数: 15/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 32-QFN
标准包装: 2,500
系列: PolyPhase®
PWM 型: 电流模式
输出数: 2
占空比: 90%
电源电压: 4 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
LTC3708
APPLICATIONS INFORMATION
L = ?
PLL and Frequency Synchronization
In the LTC3708, there are two onboard phase-locked loops
(PLL). One PLL is used to achieve frequency locking and
180° phase shift between the two channels while the sec-
ond PLL locks onto the rising edge of an external clock.
Since the LTC3708 uses a constant on-time architecture,
the error signal generated by the phase detector of the PLL
is used to vary the on time to achieve frequency locking
and phase separation. The variable on-time range is from
0.5 ? t ON to 2 ? t ON , where t ON is the initial on time set by
the R ON resistor.
To fully utilize the frequency synchronization range of the
PLL, it is advisable to set the initial on time properly so
that the two channels have close free-running frequencies.
Frequencies far apart may exceed the synchronization
capability of the PLL. If the two output voltages are V OUT1
and V OUT2 , for example, R ON resistors should then be
selected proportionally:
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and ripples in the
output voltage. Highest ef?ciency operation is obtained at
low frequency with small ripple current. However, achieving
this requires a large inductor. There is a trade-off between
component size and ef?ciency.
A reasonable starting point is to choose a ripple current
that is about 40% of I OUT(MAX) . Note that the largest ripple
current occurs at the highest V IN . To guarantee that ripple
current does not exceed a speci?ed maximum, the induc-
tance should be chosen according to:
? V OUT ? ? V OUT ?
? ? ?
? f ? Δ I L ( MAX ) ? ? 1 – V IN ( MAX ) ?
Once the value for L is known, the type of inductor must be
selected. A variety of inductors designed for high current,
low voltage applications are available from manufacturers
such as Sumida and Panasonic.
= OUT 1
R ON1
R ON 2
V
V OUT 2
Schottky Diode Selection
Similarly, if the external PLL is engaged to synchronize
to an external frequency of f EXT , R ON1 should be selected
close to:
The Schottky diodes in parallel with both bottom MOSFETs
conduct during the dead time between the conduction of
the power MOSFET switches. They are intended to prevent
the body diode of the bottom MOSFET from turning on
R ON 1 =
V OUT 1
0 . 7 ? f EXT ? 10 pF
and storing charge during the dead time, which causes a
modest (about 1%) ef?ciency loss. The diodes can be rated
for about one-half to one-?fth of the full load current since
hence, ? R ON2 =
0 . 7 ? f EXT ? 10 pF ?
?
?
V OUT 2 ?
?
they are on for only a fraction of the duty cycle. In order
for the diodes to be effective, the inductance between them
and the bottom MOSFETs must be as small as possible,
Δ I L = ? OUT ? ? 1 – OUT ?
In this case, channel 1 will ?rst be synchronized to the
external frequency and channel 2 will then be synchronized
to channel 1 with 180° phase separation.
Inductor Selection
Given the desired input and output voltages, the induc-
tor value and operating frequency determine the ripple
current:
? V ? ? V ?
? f ? L ? ? V IN ?
mandating that these components be placed as close as
possible in the circuit board layout. The diodes can be
omitted if the ef?ciency loss is tolerable.
C IN and C OUT Selection
The selection of C IN is simpli?ed by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case RMS current occurs when
only one controller is operating. The controller with the
3708fb
15
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