参数资料
型号: LTC3713EG
厂商: Linear Technology
文件页数: 19/24页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 24-SSOP
标准包装: 59
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 90%
电源电压: 1.5 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-SSOP(0.209",5.30mm 宽)
包装: 管件
LTC3713
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out a PC board follow one of the two
suggested approaches. The simple PC board layout
requires a dedicated ground plane layer. Also, for higher
currents, it is recommended to use a multilayer board to
help with heat sinking power components.
? The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
? Place C IN , C OUT , MOSFETs, D1 and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
? Place LTC3713 chip with Pins 13 to 24 facing the
power components. Keep the components connected
to Pins 1 to 12 close to LTC3713 (noise sensitive
components).
? Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3713.
Use several bigger vias for power components.
? Use a compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
? Use planes for V IN and V OUT to maintain good voltage
filtering and to keep power losses low.
? Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power component. You can connect the copper
areas to any DC net (V IN , V OUT , GND or to any other DC
rail in your system).
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller. These items are also illustrated in
Figure 8.
? Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.
? Place M2 as close to the controller as possible, keep-
ing the PGND, BG and SW traces short.
? Connect the input capacitor(s) C IN close to the power
MOSFETs. This capacitor carries the MOSFET AC
current.
? Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
? Connect the INTV CC decoupling capacitor C VCC closely
to the INTV CC and PGND pins.
? Connect the top driver boost capacitor C B closely to
the BOOST and SW pins.
C SS
1
RUN/SS
BOOST
24
+
V IN
2
3
4
V ON
PGOOD
V RNG
TG
SW1
SENSE +
23
22
21
D B
C B
M1
L1
C IN
V OUT
SENSE
C1
R C
5
6
FCB
I TH
PGND1
20
19
M2
D2
C OUT
C2
7
LTC3713
SGND1
BG
18
R F2
R F1
R ON
8
9
10
11
I ON
V FB1
SHDN
SGND2
INTV CC
V IN1
V IN2
PGND2
17
16
15
14
C IN2
C VCC
L2
3713 F08
BOLD LINES INDICATE HIGH CURRENT PATHS
R F3
R F5
12
V FB2
R F4
SW2
13
D3
Figure 8. LTC3713 Layout Diagram
3713fa
19
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