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| 型号： | LTC3717EUH-1#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR STEP-DOWN SYNC 32QFN |
| 标准包装： | 73 |
| 应用： | 控制器，DDR，QDR |
| 输入电压： | 4 V ~ 36 V |
| 输出数： | 1 |
| 输出电压： | 2 V ~ 18 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
| 产品目录页面： | 1335 (CN2011-ZH PDF) |
LTC3717-1
APPLICATIO S I FOR ATIO
I LIMIT ≥
+ ( 3 . 7 A ) = 12 . 1 A
=
( 12 . 1 A ) ( 1 . 4 )( 0 . 010 ? ) = 1 . 02 W
2 . 5 V – 1 . 25 V
P BOT
TyingV RNG to1.1V willsetthecurrentsensevoltagerange
for a nominal value of 110mV with current limit occurring
at 143mV. To check if the current limit is acceptable,
assume a junction temperature of about 40 ° C above a
70 ° C ambient with ρ 110 ° C = 1.4:
143 mV 1
( 1 . 4 )( 0 . 010 ? ) 2
and double check the assumed T J in the MOSFET:
2
2 . 5 V
T J = 70 ° C + (1.02W)(40 ° C/W) = 111 ° C
Because the top MOSFET is on roughly the same amount
of time as the bottom MOSFET, the same Si4874 can be
used as the synchronous MOSFET.
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
C IN is chosen for an RMS current rating of about 5A at
85 ° C. The output capacitors are chosen for a low ESR of
0.013 ? to minimize output voltage changes due to induc-
tor ripple current and load steps. For current sinking
applications where current flows back to the input through
the top transistor, output capacitors with a similar amount
of bulk C and ESR should be placed on the input as well.
(This is typically the case, since V IN is derived from
another DC/DC converter.) The ripple voltage will be only:
? V OUT(RIPPLE) = ? I L(MAX) (ESR)
= (4A) (0.013 ? ) = 52mV
However, a 0A to 10A load step will cause an output
change of up to:
? V OUT(STEP) = ? I LOAD (ESR) = (10A) (0.013 ? ) = 130mV
An optional 22 μ F ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 7.
PC Board Layout Checklist
When laying out a PC board follow one of the two sug-
gested approaches. The simple PC board layout requires
a dedicated ground plane layer. Also, for higher currents,
it is recommended to use a multilayer board to help with
heat sinking power components.
C SS
0.1 μ F
D B
CMDSH-3
R3 R4
11k 39k
C C1
470pF R C
20k
C C2
100pF
R PG
100k
RUN/SS BOOST
PGOOD TG
LTC3717-1
V RNG SW
SENSE +
I TH PGND
SENSE –
SGND BG
C B
0.22 μ F
M1
Si4874
M2
Si4874
D2
B320A
L1
0.68 μ H
D1
B320A
+
C IN
22 μ F
6.3V
X7R
C OUT1-2
270 μ F
2V
× 2
+
C IN
180 μ F
4V
× 2
C OUT3
22 μ F
6.3V
X7R
V IN = 2.5V
V OUT
1.25V
± 10A
C ON 0.01 μ F
V ON
I ON
INTV CC
C VCC
4.7 μ F
R ON
511k
(OPT)
0.1 μ F
V FB
V REF
DRV CC
V CC
EXTV CC
10 ?
R F
1 ?
C F
0.1 μ F
V EXT 5V
37171 F07
C IN , C OUT1-2 : CORNELL DUBILIER ESRE181E04B
L1: SUMIDA CEP125-0R68MC-H
Figure 7. Design Example: 1.25V/ ± 10A at 250kHz
sn37171 37171fs
16
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