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| 型号： | LTC3717EUH-1#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR STEP-DOWN SYNC 32QFN |
| 标准包装： | 73 |
| 应用： | 控制器，DDR，QDR |
| 输入电压： | 4 V ~ 36 V |
| 输出数： | 1 |
| 输出电压： | 2 V ~ 18 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
| 产品目录页面： | 1335 (CN2011-ZH PDF) |
LTC3717-1
APPLICATIO S I FOR ATIO
? The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
? Place C IN , C OUT , MOSFETs, D1 and inductor all in one
compact area. It may help to have some components on
the bottom side of the board.
? Place LTC3717-1 chip with Pins 15 to 28 facing the
power components. Keep the components connected
to Pins 1 to 10 close to LTC3717-1 (noise sensitive
components).
? Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3717-1.
Use several bigger vias for power components.
? Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
? Use planes for V IN and V OUT to maintain good voltage
filtering and to keep power losses low.
? Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power component. You can connect the copper areas to
any DC net (V IN , V OUT , GND or to any other DC rail in
your system).
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller. These items are also illustrated in
Figure 8.
? Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
source of M2.
? Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
? Connect the input capacitor(s) C IN close to the power
MOSFETs. This capacitor carries the MOSFET AC cur-
rent.
? Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
? Connect the INTV CC and DRV CC decoupling capacitor
C VCC closely to the INTV CC , DRV CC and PGND pins.
? Connect the top driver boost capacitor C B closely to the
BOOST and SW pins.
? Connect the V CC pin decoupling capacitor C F closely to
the V CC and PGND pins.
C SS
RUN/SS
BOOST
PGOOD
TG
LTC3717-1
C B
D B
L
C C1
R C
V RNG
SW
SENSE +
M1
+
I TH
PGND
C C2
SENSE –
D2
V IN
C ION
SGND
V ON
BG
C VCC
M2
D1
C IN
–
I ON
INTV CC
C FB
DRV CC
–
V FB
V REF
V CC
EXTV CC
C F
R F
C OUT
+
V OUT
R ON
BOLD LINES INDICATE HIGH CURRENT PATHS
37171 F08
Figure 8. LTC3717-1 Layout Diagram
sn37171 37171fs
17
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