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参数资料
| 型号： | LTC3733CUHF-1#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 15/32页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK 3PH AMD CPU 38-QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，AMD |
| 输入电压： | 4 V ~ 36 V |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 1.55 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 供应商设备封装： | 38-QFN（5x7） |
| 包装： | 带卷 (TR) |
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LTC3733/LTC3733-1
APPLICATIO S I FOR ATIO
V IN
The power dissipation for the main and synchronous
V GS
MILLER EFFECT
V
V DS
MOSFETs at maximum output current are given by:
a
b
V OUT ? I MAX ?
? ( 1 + δ ) R DS ( ON ) +
V IN ? N ?
Q IN
C MILLER = (Q B – Q A )/V DS
V GS
3733 F05
P MAIN =
?
2
V IN 2 MAX ( R DR )( C MILLER ) ?
? ( )
? I
?
V – V
P SYNC = IN OUT ? MAX ? ( 1 + δ ) R DS ( ON )
Figure 5. Gate Charge Characteristic
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the gate-
to-drain capacitance. The flat portion of the curve is the
result of the Miller capacitance effect of the drain-to-
source capacitance as the drain drops the voltage across
the current source load. The upper sloping line is due to
the drain-to-gate accumulation capacitance and the gate-
to-source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given V DS drain voltage, but can be
adjusted for different V DS voltages by multiplying by the
ratio of the application V DS to the curve specified V DS
values. A way to estimate the C MILLER term is to take the
change in gate charge from points a and b on a manufac-
turers data sheet and divide by the stated V DS voltage
specified. C MILLER is the most important selection criteria
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. C RSS
and C OS are specified sometimes but definitions of these
parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
I
2 N
? 1 1 ?
? + f
? ?
? V CC – V TH ( MIN ) V TH ( MIN ) ?
2
V IN ? N ?
where N is the number of output stages, δ is the tempera-
ture dependency of R DS(ON) , R DR is the effective top driver
resistance (approximately 2 ? at V GS = V MILLER ), V IN is the
drain potential and the change in drain potential in the
particular application. V TH(MIN) is the data sheet specified
typical gate threshold voltage specified in the power
MOSFET data sheet. C MILLER is the calculated capacitance
using the gate charge curve from the MOSFET data sheet
and the technique described above.
Both MOSFETs have I 2 R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V IN < 12V, the
high current efficiency generally improves with larger
MOSFETs, while for V IN > 12V, the transition losses
rapidly increase to the point that the use of a higher
R DS(ON) device with lower C RSS actually provides higher
efficiency. The synchronous MOSFET losses are greatest
Main Switch Duty Cycle =
V OUT
V IN
at high input voltage when the top switch duty factor is low
or during a short circuit when the synchronous switch is
on close to 100% of the period.
Synchronous Switch Duty Cycle = ? IN OUT ?
? V – V ?
? V IN ?
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized R DS(ON) vs temperature curve, but
3733f
15
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