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参数资料
| 型号： | LTC3733CUHF-1#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 20/32页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK 3PH AMD CPU 38-QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，AMD |
| 输入电压： | 4 V ~ 36 V |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 1.55 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 供应商设备封装： | 38-QFN（5x7） |
| 包装： | 带卷 (TR) |
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LTC3733/LTC3733-1
APPLICATIO S I FOR ATIO
Fault Conditions: Overcurrent Latchoff
The SS pin also provides the ability to latch off the
controllers when an overcurrent condition is detected. The
SS capacitor is used initially to limit the inrush current of
all three output stages. After the controllers have been
given adequate time to charge up the output capacitor and
provide full load current, the SS capacitor is used for a
short-circuit timer. If the output voltage falls to less than
70% of its nominal value, the SS capacitor begins dis-
charging on the assumption that the output is in an
overcurrent condition. If the condition lasts for a long
enough period, as determined by the size of the SS
capacitor, the controller will be shut down until the RUN
pin voltage is recycled. If the overload occurs during start-
up, the time can be approximated by:
t LO1 >> (C SS ? 0.6V)/(1.5 μ A) = 4 ? 10 5 (C SS )
If the overload occurs after start-up, the voltage on the SS
capacitor will continue charging and will provide addi-
tional time before latching off:
t LO2 >> (C SS ? 3V)/(1.5 μ A) = 2 ? 10 6 (C SS )
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the SS pin from V CC as
shown in Figure 7. When V CC is 5V, a 200k resistance will
prevent the discharge of the SS capacitor during an
overcurrent condition but also shortens the soft-start
period, so a larger SS capacitor value will be required.
Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem with
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
foldback current limiting still remains active, thereby
protecting the power supply system from failure. A deci-
sion can be made after the design is complete whether to
rely solely on foldback current limiting or to enable the
latchoff feature by removing the pull-up resistor.
The value of the soft-start capacitor C SS may need to be
scaled with output current, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
C SS > (C OUT )(V OUT ) (10 –4 ) (R SENSE )
The minimum recommended soft-start capacitor of
C SS = 0.1 μ F will be sufficient for most applications.
Current Foldback
In certain applications, it may be desirable to defeat the
internal current foldback function. A negative impedance
is experienced when powering a switching regulator.
That is, the input current is higher at a lower V IN and
decreases as V IN is increased. Current foldback is de-
signed to accommodate a normal, resistive load having
increasing current draw with increasing voltage. The EAIN
pin should be artificially held 70% above its nominal
operating level of 0.6V, or 0.42V in order to prevent the IC
from “folding back” the peak current level. A suggested
circuit is shown in Figure 8.
noise pick-up or poor layout causing the protection circuit
V CC
V CC
V CC
R SS
SS PIN
CALCULATE FOR
Q1
EAIN
LTC3733
0.42V TO 0.55V
C SS
3733 F07
Figure 7. Defeating Overcurrent Latchoff
3733 F08
Figure 8. Foldback Current Elimination
3733f
20
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